JPS57146349A - Discriminating method of performance of check circuit - Google Patents

Discriminating method of performance of check circuit

Info

Publication number
JPS57146349A
JPS57146349A JP56031531A JP3153181A JPS57146349A JP S57146349 A JPS57146349 A JP S57146349A JP 56031531 A JP56031531 A JP 56031531A JP 3153181 A JP3153181 A JP 3153181A JP S57146349 A JPS57146349 A JP S57146349A
Authority
JP
Japan
Prior art keywords
data
error
read
area
performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56031531A
Other languages
Japanese (ja)
Inventor
Shuhei Yasuda
Yukio Nakagawa
Shosaku Furubayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP56031531A priority Critical patent/JPS57146349A/en
Publication of JPS57146349A publication Critical patent/JPS57146349A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/277Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To minimize the working time accompanied by the discrimination of performance, by storing data changed intentionally to a storage device and executing the discrimination of performance of a check circuit with this data with a program. CONSTITUTION:When a diagnostic write instruction is generated, a designated data is written in a data area M1 of a storage device 2. Check information changed intentionally to generate a parity error or an error correction check ECC error is written in a check information area M2. Next, when a read instruction is produced, data are read in from the area M1 and the check information accompanied by the data is read in from the area M2. If an error is detected from the read-in data by checking 3 both the data, an error detecting signal is outputted. In case of the ECC circuit, the error correction processing is quickly performed for the data.
JP56031531A 1981-03-05 1981-03-05 Discriminating method of performance of check circuit Pending JPS57146349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56031531A JPS57146349A (en) 1981-03-05 1981-03-05 Discriminating method of performance of check circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56031531A JPS57146349A (en) 1981-03-05 1981-03-05 Discriminating method of performance of check circuit

Publications (1)

Publication Number Publication Date
JPS57146349A true JPS57146349A (en) 1982-09-09

Family

ID=12333774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56031531A Pending JPS57146349A (en) 1981-03-05 1981-03-05 Discriminating method of performance of check circuit

Country Status (1)

Country Link
JP (1) JPS57146349A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426938A (en) * 1987-07-23 1989-01-30 Fujitsu Ltd Test system for ras circuit
JPH0414148A (en) * 1990-05-08 1992-01-20 Yamatake Honeywell Co Ltd Test method for parity check circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159933A (en) * 1974-06-14 1975-12-24
JPS5280755A (en) * 1975-12-27 1977-07-06 Toshiba Corp Testing method for error correction circuit
JPS54122937A (en) * 1978-03-16 1979-09-22 Nec Corp Memory unit
JPS5583946A (en) * 1978-12-21 1980-06-24 Toshiba Corp Diagnosis system for data error detection/correction circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159933A (en) * 1974-06-14 1975-12-24
JPS5280755A (en) * 1975-12-27 1977-07-06 Toshiba Corp Testing method for error correction circuit
JPS54122937A (en) * 1978-03-16 1979-09-22 Nec Corp Memory unit
JPS5583946A (en) * 1978-12-21 1980-06-24 Toshiba Corp Diagnosis system for data error detection/correction circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426938A (en) * 1987-07-23 1989-01-30 Fujitsu Ltd Test system for ras circuit
JPH0414148A (en) * 1990-05-08 1992-01-20 Yamatake Honeywell Co Ltd Test method for parity check circuit

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