JPS57169857A - Control storage device - Google Patents
Control storage deviceInfo
- Publication number
- JPS57169857A JPS57169857A JP56055260A JP5526081A JPS57169857A JP S57169857 A JPS57169857 A JP S57169857A JP 56055260 A JP56055260 A JP 56055260A JP 5526081 A JP5526081 A JP 5526081A JP S57169857 A JPS57169857 A JP S57169857A
- Authority
- JP
- Japan
- Prior art keywords
- control storage
- error
- storage device
- control
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE:To continue normal processing without reducing a speed even in case of an error in control storage and an uncorrectable error, by adding an error correction code to control storage and lapping the execution of instructions and error checking. CONSTITUTION:Once receiving an uncorrectable signal from a control storage device 4, a service processor 2 reads a control storage address backup register (BMAR,9) stored with error instruction addresses, and then reads correct microin struction data out of an external storage device 3 and sets it in a control storage data write register (WMDR,10). Further, a control signal to be set in a CMAR6 is outputted, and the rewritten microinstruction of the CMAR6 is read out and set in a control storage data register CMDR7, executing the microinstruction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56055260A JPS57169857A (en) | 1981-04-13 | 1981-04-13 | Control storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56055260A JPS57169857A (en) | 1981-04-13 | 1981-04-13 | Control storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57169857A true JPS57169857A (en) | 1982-10-19 |
Family
ID=12993619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56055260A Pending JPS57169857A (en) | 1981-04-13 | 1981-04-13 | Control storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57169857A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59148954A (en) * | 1983-02-14 | 1984-08-25 | Fujitsu Ltd | Patrolling system of control storage |
JPS59174952A (en) * | 1983-03-24 | 1984-10-03 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Recovery of parity error |
JPS59174951A (en) * | 1983-03-25 | 1984-10-03 | Fujitsu Ltd | System for correcting 2-bit error of control memory |
JPS61175820A (en) * | 1985-01-31 | 1986-08-07 | Fujitsu Ltd | Controlling system of micro-instruction |
JPH0375834A (en) * | 1989-05-22 | 1991-03-29 | Tandem Comput Inc | Apparatus and method of sequentially correcting parity |
-
1981
- 1981-04-13 JP JP56055260A patent/JPS57169857A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59148954A (en) * | 1983-02-14 | 1984-08-25 | Fujitsu Ltd | Patrolling system of control storage |
JPS59174952A (en) * | 1983-03-24 | 1984-10-03 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Recovery of parity error |
JPH0325814B2 (en) * | 1983-03-24 | 1991-04-09 | Intaanashonaru Bijinesu Mashiinzu Corp | |
JPS59174951A (en) * | 1983-03-25 | 1984-10-03 | Fujitsu Ltd | System for correcting 2-bit error of control memory |
JPS6341095B2 (en) * | 1983-03-25 | 1988-08-15 | Fujitsu Ltd | |
JPS61175820A (en) * | 1985-01-31 | 1986-08-07 | Fujitsu Ltd | Controlling system of micro-instruction |
JPH0375834A (en) * | 1989-05-22 | 1991-03-29 | Tandem Comput Inc | Apparatus and method of sequentially correcting parity |
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