JPS648452A - Microprogram control device - Google Patents

Microprogram control device

Info

Publication number
JPS648452A
JPS648452A JP62164250A JP16425087A JPS648452A JP S648452 A JPS648452 A JP S648452A JP 62164250 A JP62164250 A JP 62164250A JP 16425087 A JP16425087 A JP 16425087A JP S648452 A JPS648452 A JP S648452A
Authority
JP
Japan
Prior art keywords
microinstruction
result
parity bit
outputted
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164250A
Other languages
Japanese (ja)
Inventor
Katsu Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62164250A priority Critical patent/JPS648452A/en
Publication of JPS648452A publication Critical patent/JPS648452A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To omit a parity check circuit and a suppressing circuit and to reduce the number of hardwares by constituting a decoder so that contents read out from a control record storing a microinstruction and a parity bit added to the microinstruction can be uniformly decoded. CONSTITUTION:In response to the control memory 10 in which a microinstruction and a parity bit added to the instruction area previously written, the contents, i.e., the microinstruction and the parity bit, stored in an address specified by an address signal A are simultaneously read out by a microinstruction register 11. The read instruction bits m0, m1 and the parity bit P are decoded by a decoder 12, and the result is correct, the result is outputted as instruction bits M0-M3. In case of an incorrect result, the result is outputted as a jump instruction to an error processor. Since only a parity detecting gate outputs a signal and no output is generated from a microinstruction gate, the microinstruction is not outputted.
JP62164250A 1987-06-30 1987-06-30 Microprogram control device Pending JPS648452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164250A JPS648452A (en) 1987-06-30 1987-06-30 Microprogram control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164250A JPS648452A (en) 1987-06-30 1987-06-30 Microprogram control device

Publications (1)

Publication Number Publication Date
JPS648452A true JPS648452A (en) 1989-01-12

Family

ID=15789528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164250A Pending JPS648452A (en) 1987-06-30 1987-06-30 Microprogram control device

Country Status (1)

Country Link
JP (1) JPS648452A (en)

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