JPS56111950A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS56111950A
JPS56111950A JP1479380A JP1479380A JPS56111950A JP S56111950 A JPS56111950 A JP S56111950A JP 1479380 A JP1479380 A JP 1479380A JP 1479380 A JP1479380 A JP 1479380A JP S56111950 A JPS56111950 A JP S56111950A
Authority
JP
Japan
Prior art keywords
control memory
bit
error detection
ecc
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1479380A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1479380A priority Critical patent/JPS56111950A/en
Publication of JPS56111950A publication Critical patent/JPS56111950A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To ensure an error detection when a control memory is read out regarding an optional address, by writing with inversion the bit designated among the ECC codes produced from the ECC generating circuit into a control memory when a microinstruction is written into the control memory. CONSTITUTION:The control memory write data is set to the microinstruction register 120 when a microprogram is written into the control memory 100. Then the ECC code is produced at the error detection/correction circuit 200 for the write data mentioned above, and either this code bit or its reverse bit is selected by the selection gate 222 and by an indication given from the check bit reverse flag generating means 230 to be written into the memory 100 along with the control memory data. Both the control memory data and the ECC code including the reverse bit are read out in the read mode, and an error detection is given by the circuit 200. If the error detecting action is correct, are error is detected in the control data to which the ECC code including the reverse bit is added. In such way, the normal operation is confirmed easily for an error detection.
JP1479380A 1980-02-12 1980-02-12 Microprogram controller Pending JPS56111950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1479380A JPS56111950A (en) 1980-02-12 1980-02-12 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1479380A JPS56111950A (en) 1980-02-12 1980-02-12 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS56111950A true JPS56111950A (en) 1981-09-04

Family

ID=11870924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1479380A Pending JPS56111950A (en) 1980-02-12 1980-02-12 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS56111950A (en)

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