JPS59109950A - Error processing system of control storage device - Google Patents
Error processing system of control storage deviceInfo
- Publication number
- JPS59109950A JPS59109950A JP57219727A JP21972782A JPS59109950A JP S59109950 A JPS59109950 A JP S59109950A JP 57219727 A JP57219727 A JP 57219727A JP 21972782 A JP21972782 A JP 21972782A JP S59109950 A JPS59109950 A JP S59109950A
- Authority
- JP
- Japan
- Prior art keywords
- parity
- storage device
- mode
- parity bit
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
Abstract
PURPOSE:To change easily the contents of a control storage, and to simplify a validity check by changing a parity bit storage device of a control storage device of a data processing device so as to be rewritable, and rewriting it by a micro-instruction. CONSTITUTION:When a power source is turned on to a device, a mode control device 29 of a parity check is set to a parity generating mode, and a value of a parity bit added to a read-only memory device 21 by a micro-instruction is written successively in a parity bit storage device 22. Subsequently, when the mode controlling circuit 29 of a parity check is set to a parity check mode, and an address of the parity bit storage device 22 in which an erroneous parity bit is written is read out, a parity error is detected by a parity checking circuit 23, and a parity error signal 25 is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57219727A JPS59109950A (en) | 1982-12-15 | 1982-12-15 | Error processing system of control storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57219727A JPS59109950A (en) | 1982-12-15 | 1982-12-15 | Error processing system of control storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59109950A true JPS59109950A (en) | 1984-06-25 |
Family
ID=16740020
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57219727A Pending JPS59109950A (en) | 1982-12-15 | 1982-12-15 | Error processing system of control storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59109950A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638733U (en) * | 1991-11-28 | 1994-05-24 | 稔 大石 | Removable baby mat cover |
-
1982
- 1982-12-15 JP JP57219727A patent/JPS59109950A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0638733U (en) * | 1991-11-28 | 1994-05-24 | 稔 大石 | Removable baby mat cover |
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