JPS6125259A - Rewriting control system of memory - Google Patents

Abstract

PURPOSE:To perform the recovery of a soft error with no inhibition of other requests to a memory by carrying out a partial writing action for rereading and rewriting actions for recovery of the soft error when a correctable error is detected. CONSTITUTION:When a correctable error is detected by a decoding circuit 21 through a reading action given from a memory array 19, both a read information selection control register 3 and a write request register 2 are set at ''1''. Then a rewriting action is commanded to an address where an error is detected. In this case, an AND gate 4 is closed by the register 3 and a partial write designating signal is set to a partial write designating register with its 8 bits all set at ''0''. Therefore, a partial write control circuit 15 is started via gates 11 and 12 for execution of a partial writing action. Then only 8 bytes of the read information obtained via the circuit 21 are selected by a partial write uniting circuit 17 and then written again on the array 19 via a coding circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a storage device using a semiconductor memory, and particularly to a rewrite control method suitable for repairing soft errors thereof.

[Background of the invention]

When a correctable error is detected during reading from a storage device using a semiconductor memory, the error-corrected read information is used as rewrite information to repair the soft error. Rewriting to the address where an error has been detected is widely and generally performed.

In this rewriting, a read request is first issued to the address where the error has occurred, and corrected data is written in using a write request. In this case, it is necessary to control the address so that it is not rewritten between the time when the readout information for generating the rewrite location information is read and the time when the rewrite is performed. For this reason, conventionally, when a correctable error is detected, all other requests to the storage device are prohibited, and reading from the address and writing are performed again. In the conventional rewrite control method, the storage device cannot be used until the series of rereading and rewriting is completed. (processing device, input/output processing device, etc.), processing may be interrupted.

[Purpose of the invention]

An object of the present invention is to provide a rewrite control method suitable for repairing soft errors that reduces such conventional problems.

[Summary of the invention]

The present invention provides a storage device having a partial write control circuit that performs writing by merging write information and read information using a partial write designation signal, in which the partial write designation signal is controlled to select read information. and means for activating the partial write control circuit in response to a write operation request in which all partial write designation signals select read information. When detected, all partial write designation signals are controlled to select read information, and rewriting is performed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In this figure, 1 is a read request register for the storage device; 2 is a read request register for the storage device;
is the write request register.

Reference numeral 3 indicates a read information selection control register, and 4 indicates an MO gate.

Eight-bit partial write designation signals are controlled to select read information. 5 is an 8-bit partial write designation signal register, 6 to 7 and 10°12 are AND gates,
8 is an OR gate, 9 is a NOR gate, 11 is a NAND gate, 13 is a read control circuit, 14 is a full write control circuit, 1
5 indicates a partial write control circuit. Here, read control circuit 1
3 is activated by the read request register 1, and the full write control circuit 14 is activated when the partial write designation signal register 5 is all 1'.

It is activated by write request register 2 via gates 6-7. When one or more partial write designation signal registers 5 are ``1'' and one or more are ``0'', the partial write control circuit 15 outputs a partial write command from the write request register 2 via gates 8 to 10. When the designation signal register 5 is all 0', it is activated by the write request register 2Vc via gates 11-12. Also, 16 is an 8-byte (72-bit) write information register, 17 is a partial write merging circuit, 18 is an encoding circuit, 19 is a memory array, 20 is an 8-byte (72-bit) read information register, and 21 is an 8-byte (72-bit) read information register. A decoding circuit is shown. The partial write merging circuit 17 selects either the write information of the write information register 16 or the read information via the decoding circuit 21 for each byte from the partial write designation signal register 51C of the byte. In this embodiment, when the partial write designation signal register 5 is 1', write information is selected, and when it is 0', read information is selected. The read control circuit 15 is connected to the memory array 1
9, the read information register 20, and the decoding circuit 21 are activated to execute the read operation. The full write control circuit 14 activates the partial write merging circuit 17, the encoding circuit 18, and the memory array 19, and issues a memory array 1qvc write command (hereinafter referred to as function) to execute the full write operation. The partial write control circuit 15 includes a memory array 19 and a read information register 20.
, decoding circuit 21, partial write merging circuit 17. While activating the encoding circuit 18, the memory array 196CWE
to execute a partial write operation. Now, in FIG. 1, when a correctable error is detected in the decoding circuit 21 during reading from the memory array 19, the processing unit (
The read information selection control register 3 and the write request register 2 are reset to '1' by a microprogram (not shown), and rewriting to the address where the error was detected is commanded. At this time, the partial write designation signal is set by the read information selection control register 5vc when the ANDNO gate i is closed, all 8 bits become 0', and the partial write designation signal register 5vc is set. As a result, gate 11~
Partial write control circuit 15 is activated via 12, and a partial write operation is executed. At this time, partial write merging circuit 17
In this case, since the partial write designation signal register 5 is all 0', only the 8 bytes of read information via the decoding circuit 21 are selected and rewritten to the memory array 19 via the encoding circuit 18.

〔Effect of the invention〕

According to the present invention, when a correctable error is detected in reading from a storage device, rereading and rewriting for soft error recovery can be performed by partial write operation (1) The address is not rewritten between the time the read information is read to generate the rewrite information and the information is rewritten, and other requests to the storage device can be executed without being inhibited.

(2) It is possible to execute the process simply by issuing the complimentary operation request r, and it is possible to move on to the next process without waiting for the completion of the process.

(8) It becomes possible to execute the access request with a lower priority than other access requests.

As a result, it is possible to realize rewriting for correcting a soft error while preventing a decrease in the performance of the processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device showing one embodiment of the present invention. 1... Read request register 2... Write request register 3... Read information selection control register 5... Partial write designation signal register 13... Read control circuit 14... Full write control circuit 15 ...Partial write control circuit 16...Write information visitor 17...Partial write merge circuit 18...Encoding circuit 19...Memory array 20...Read information register 21...Decoding circuit

Claims (1)

[Claims] 1. In a storage device having a partial write control circuit that performs writing by merging write information and read information using a partial write designation signal, means for controlling the partial write designation signal to select read information. characterized in that when an error is detected, the partial write control circuit is activated to perform rewriting in response to a write operation request in which all partial write designation signals select read information. A rewrite control method for storage devices.