JPS56117400A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS56117400A JPS56117400A JP2086380A JP2086380A JPS56117400A JP S56117400 A JPS56117400 A JP S56117400A JP 2086380 A JP2086380 A JP 2086380A JP 2086380 A JP2086380 A JP 2086380A JP S56117400 A JPS56117400 A JP S56117400A
- Authority
- JP
- Japan
- Prior art keywords
- data
- error
- bit
- tag data
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 abstract 2
- 230000004075 alteration Effects 0.000 abstract 1
- 230000001276 controlling effect Effects 0.000 abstract 1
- 230000000875 corresponding Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Abstract
PURPOSE:To make the correction of data and tag data without making the constitution complicated and without increasing the buffer access time, by controlling the status of ineffective bit of data at the detection of parity error of data or tag data at buffer access. CONSTITUTION:If the data read out from the data 5 has error, the error register 14 is set with the parity check circuit 10 and the error is set to the instruction unit. Further, the set number indicating the error detecting position is set to the error address register 27 to inhibit the access from the instruction unit, and if the alteration bit in the tag data corresponding to the data of error detection is OFF, the content of the effective address register 1 is corrected with the register 27 to make ON the ineffective bit of the tag data. In case of ON, the data is corrected, the ineffective bit is made ON, and correction is made with shorter access time with a simple constitution through the control based on the parity check only the same as the tag data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55020863A JPS6223901B2 (en) | 1980-02-20 | 1980-02-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55020863A JPS6223901B2 (en) | 1980-02-20 | 1980-02-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56117400A true JPS56117400A (en) | 1981-09-14 |
JPS6223901B2 JPS6223901B2 (en) | 1987-05-26 |
Family
ID=12038967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55020863A Expired JPS6223901B2 (en) | 1980-02-20 | 1980-02-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6223901B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6473433A (en) * | 1987-09-16 | 1989-03-17 | Fujitsu Ltd | Cache memory control system |
JPH0223442A (en) * | 1988-07-13 | 1990-01-25 | Nec Corp | Memory control device |
-
1980
- 1980-02-20 JP JP55020863A patent/JPS6223901B2/ja not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6473433A (en) * | 1987-09-16 | 1989-03-17 | Fujitsu Ltd | Cache memory control system |
JPH0223442A (en) * | 1988-07-13 | 1990-01-25 | Nec Corp | Memory control device |
Also Published As
Publication number | Publication date |
---|---|
JPS6223901B2 (en) | 1987-05-26 |
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