JPS62127944A - Information processor - Google Patents

Abstract

PURPOSE:To control run away of a program due to an error occurred by deciding whether each instruction is a definition program or not when an initial program and programs discrimination data are read out from a storage section by an arithmetic controlling section. CONSTITUTION:A definition bit verification circuit 8 judges that an instruction corresponding to program definition 9 is a definition program when a program definition bit 10 is recognized as '1', and judges that the instruction corresponding to the program definition bit 10 is an undefined programs when the program definition bit 10 is recognized as '0' and outputs an alarm signal 11 that indicates program abnormality. The definition bit verification circuit 8 outputs a driving stop command signal to an arithmetic processing section 5 in synchronization with outputting of the alarm signal 11 that indicates program abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to an information processing device, and more particularly to an information processing device equipped with a function to prevent runaway programs.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional information processing device equipped with a program error detection function.

In Figure 3, (1) is the main memory, (2) is the information bus, and (3) is the central processing unit (hereinafter referred to as rCPUJ).
, (4) is the instruction register, (5) is the arithmetic processing unit, (6)
is a monitoring circuit. The main storage device (1) described above contains a control program and the like, and also stores necessary data. The main storage device (1) stores the own address jump instruction written to the entire storage area by the CPU (3) under the control of the CPU (3) mentioned above, and also stores the own address jump instruction written in the entire storage area by the CPU (3) as shown in FIG. The program loaded by the CPU (3) is stored in accordance with the flowchart shown in FIG. 5 with the layout shown in FIG. The information bus (2) connects the main storage device (1) mentioned above and the CPU (3), and is used to transfer various data between the CPU (3) and the main storage device (1). It is an interface for sending and receiving. The aforementioned CPU (3) has the aforementioned instruction register (4).
), and an arithmetic processing section (5). The instruction register (4) sequentially reads the initial program stored in the main storage device (1) mentioned above and stores the predetermined period program. The arithmetic processing unit (5) performs arithmetic processing based on the program output from the instruction register (4) described above. The above-mentioned monitoring circuit (6) has a built-in watchdog timer that detects abnormalities that occur in the hardware of the information processing device, and monitors the execution status of the program by the CPU (3) as well as the monitoring circuit (6). It is configured to output an external alarm signal (7) when it is recognized that there is an abnormality as a result.

Next, the operation of the information processing apparatus configured as described above will be explained.

As shown in the flowchart of FIG. 4, first, each register and main storage device (
After performing a system clear operation to clear 1) and writing a local address jump instruction to the entire storage area of the main storage device (1), an initial program is loaded to the main storage device (1).

The own address jump instruction written in all storage areas of the main memory (1) is, for example, EOOO, and the initial program loaded into the main memory (1) is, for example, A, B,
C, D, and E, the contents stored in the main storage device (1) after the series of processes described above are completed will be in the state shown in FIG. The instruction register mentioned above (
4), when the storage contents (i.e., the initial program) as shown in FIG.
) performs arithmetic processing based on the initial program.

If the arithmetic processing unit (5) normally executes the above-mentioned initial program, the above-mentioned own address jump instruction (EO
OO) is never executed, so A, B.

Processing is performed in the order of C, D, and E. However, if a change occurs in the program load address due to external factors or a change occurs in the program load address due to a hardware error in the information processing device, the CPU (3) may change the initial program setting. When accessing a storage area of the main memory (1) that has not been accessed, the above-mentioned own address jump command EOOO is executed.
Since H is loaded into the instruction register (4), the arithmetic processing unit (5) executes the own address jump instruction. When the own address jump instruction is executed by the arithmetic processing unit (5), the execution of the own address jump instruction is detected by the watchdog timer of the above-mentioned monitoring circuit (6), and the execution of the own address jump instruction is detected from the monitoring circuit (6). An external alarm signal (7) based on the detection will be output. For details of the above-mentioned conventional technology, please refer to Japanese Patent Laid-Open No. 58-56292.

[Problem that the invention seeks to solve]

Since the conventional information processing apparatus is configured as described above, there are problems as described below.

That is, the monitoring circuit (
6), the watchdog timer was used to detect whether or not the arithmetic processing unit (5) had executed the own address jump instruction. There was a problem in that error detection could not be performed and it took a long time from when an error occurred until it was detected. In addition, since it takes time from the occurrence of an error until the error is detected by the watchdog timer, the hardware of the information processing device such as the main storage device (1), information bus (2), arithmetic processing unit (5), etc. If an error occurs due to some kind of failure, there is no guarantee that the arithmetic processing unit (5) will execute the initial program normally, so the watchdog timer cannot detect the error. There was also a problem in that the malicious program continued to be executed due to an error until it was fixed.

This invention was made to solve the above problems.1. It is an object of the present invention to provide an information processing device that can perform error detection at high speed and prevents execution of a malicious program from continuing for a long time due to an error that has occurred.

[Means for solving problems]

The information processing device according to the present invention includes, in the storage unit, identification data for identifying whether or not each instruction forming the initial program is a definition program, together with the initial program. It is stored in advance, and the arithmetic control unit, when the initial program and program identification data are read by the arithmetic control unit, determines whether each of the instructions is a definition program based on the identification data. The present invention is characterized in that it is provided with a definition program determining means for determining.

[Effect]

The definition program determination means in this invention is provided in the arithmetic control section, and when the initial program and identification data are read from the storage section by the arithmetic control section, each instruction is determined as a definition program based on the identification data. This is to determine whether or not there is.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. Note that the symbols (1) to (6) in FIG. 1 are the same as those shown in FIG. 3, so the explanation thereof will be omitted.

In FIG. 1, (8) is a definition program determining means, that is, a definition bit verification circuit. The aforementioned definition bit verification circuit (8) is arranged in the CPU (3). The definition bit verification circuit (8) allows the CPU (3) to fetch ( In synchronization with fetching an instruction (hereinafter the same applies) and storing it in the instruction register (4), the settings are made corresponding to each instruction forming the initial program (9) along with the initial program (9). Fetch the program definition bit (10). The definition bit verification circuit (8) is configured so that the above-mentioned program definition bit (10) is "
1'', the instruction corresponding to the program definition (9) is a definition program (that is, the program periodic pin) and forms an initial program (9) corresponding to (10). The instruction itself is determined to be normal), and the program definition bit (10) is determined to be “
0”, the program definition pin I-(
The instruction corresponding to 10) is an undefined program (
That is, it is determined that there is an abnormality in the instruction itself forming the initial program (9) that corresponds to the program definition bit (10), and an alarm signal (
11). The definition bit verification circuit (8) described above operates in synchronization with the output of the alarm signal (11) indicating a program abnormality.
5), a drive stop command signal is output.

The entire storage area of the main storage device (1) includes an initial program (9) having a program data area with a data width of 8 to 32 bits, as shown in FIG. A 1-bit wide program definition bit (
10) are stored respectively.

Next, the operation of the information processing apparatus configured as described above will be explained.

For example, the own address jump instruction in this embodiment is EOOO.
If H, then the own address jump instruction E000□ first clears each register and the main storage device (1) that make up the information processing device, as shown in the flowchart of FIG. 4 mentioned above. After the system clear operation is performed, the data is written to the entire storage area of the main storage device (1).

In synchronization with the writing of the own address jump instruction EOOOH into the entire storage area of the main storage device (1) mentioned above, the program definition pin (10) corresponding to the address where each instruction is stored is written with "0'' is written. As shown in FIG. 2, the aforementioned own address jump command EOOO
. At the same time, "1" is written to the program definition bit (10) corresponding to each instruction A, B, C, D, and E. Initial program (9) stored in the main storage device (1) in this way
, A, B, C, D, and E are fetched by the instruction register (4) of the CPU (3), the program definition corresponding to A, B, C, D, and E of the initial program (9) described above is The program definition bit verification circuit (8) fetches the program definition bit verification circuit (8) and assigns program definition bits corresponding to A, B, C, D, and E to each of the instructions.
(10) is identified as "1" or "02", and the definition bit verification circuit (8) determines whether the content of the program definition (1) is "1" or "02".
0), if it is determined that there is no abnormality, the above-mentioned arithmetic processing unit (5) executes the initial program (9), A, B, C, fetched by the above-mentioned instruction register (4).
Arithmetic processing will be executed according to the processing procedures specified in D and E. On the other hand, external factors or main memory (
1), a program error occurs in any of A, B, C, D, or E of the initial program (9) due to some kind of failure in the hardware of the information processing device, such as the information bus (2) or the arithmetic processing unit (5). occurs, A and B of the initial program (9)
, C, D, and E into the main memory (1),
"1" is never written to the program definition bit (10) corresponding to the instruction that caused the program error. Therefore, at the time when the instruction that caused the program error is fetched by the instruction register (4), that is, when the definition bit verification circuit (8) performs the above-mentioned load, the program definition bit (
10) At the time of fetching, the program error will be detected, and at that time, the definition bit verification circuit (8) will issue an alarm signal indicating a program abnormality (
11) is output, and the arithmetic processing section (5) also stops its driving. Therefore, even if a program error occurs for some reason, the program will be detected in a fairly short time and the arithmetic processing unit (5) will stop operating. Until the instruction register (4) fetches the own address jump instruction EOOO, shown in the figure, and the execution of the own address jump instruction EOOO (h) by the arithmetic processing unit (5) is detected by the aforementioned watchdog timer. , unlike conventional devices in which predetermined error handling is not performed, it is possible to prevent malicious programs from continuing to execute for a long time.Furthermore, even if the main memory is not loaded with the initial program (9) described above, In the storage area of the device (1), the program definition bit (10) is “1”.
If a program abnormality such as " is set to ", the CPU (3) accesses the storage area mentioned above and the own address jump instruction EOOOo is fetched by the instruction register (4), then the own address jump instruction EOOOo is fetched by the instruction register (4). Jump command EOOO.

is executed by the arithmetic processing unit (5), the execution of the own address jump instruction EOOOH by the arithmetic processing unit (5) is detected by the aforementioned watchdog timer, and an external alarm signal is generated from the watchdog timer7). will be output.

In the above-mentioned embodiment, the program error detection in the CPU (3) has been described, but substantially the same effect can be obtained even if the scope of application of the above technical idea is expanded to include microprogram error detection. Further, in the embodiment, the number of program definition bits (10) (7) is 1, but it goes without saying that a plurality of bits may be used.

〔Effect of the invention〕

As described above, according to the present invention, when the initial program and program identification data are read from the storage section by the arithmetic control section, it is determined whether each instruction is a definition program based on the identification data. This has the effect of providing an information processing device that can perform error detection at high speed and prevent runaway programs, such as continued execution of a malicious program for a long time due to an error that has occurred. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present invention, and FIG. 2 shows the storage contents stored in the main storage device (1) having the configuration shown in FIG. 1. FIG. 3 is a block diagram showing the configuration of a conventional information processing device, FIG. 4 is a flowchart showing the processing procedure for loading an initial program into the main storage device, and FIG.
The figure shows a main storage device (1) with the configuration shown in FIG. 3 above.
FIG. 2 is a diagram showing the contents stored in the memory. In the figure, (1) is the main memory, (3) is the CPU, (
4) is an instruction register, (5) is an arithmetic processing unit, (6) is a monitoring circuit, and (8) is a definition bit verification circuit. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Patent Attorney 1) Hiroshi Sawa: ・1・l (2 other people) −°′ ;+qqinterpretation th B, 5 times and °゛・sotot regular times? Tol! 5 Figure 4 Procedural amendment (voluntary) 1985 7.2 hB 1. Indication of case Patent application No. 1988-267431 2.
Title of the invention Information processing device 3, Representative of the person making the amendment Moriya Shiki 4, Agent Postal code 105 Address
"Nishishinbashi, Minato-ku, Tokyo" Item T 4 No. 10 No. 5, Detailed Description of the Invention column 6 of the specification subject to amendment, Detailed Description of the Amendment 11r is revised as follows: 61) τ[;

Claims (1)

[Claims] When the initial program is read by the arithmetic control unit from the storage section where the initial program is loaded into the storage area after the own address jump instruction pattern is written, it is determined whether or not there is an error in the initial program. In the information processing apparatus equipped with a program error detection function, the storage unit includes a memory for identifying whether each instruction forming the initial program is a definition program. Identification data is stored in advance together with the initial program, and when the initial program and program identification data are read by the calculation control unit, the calculation control unit executes each of the instructions based on the identification data. 1. An information processing apparatus comprising: a definition program determination means for determining whether or not a definition program is a definition program.