JP2000339189A - Method for detecting illegal memory access debugging device and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and efficiently detect any illegal access by setting a guard area for each task, and dynamically switching the guard area according to the switching of the task. SOLUTION: This ICE(in-circular emulator) is provided with a guard area chart 101 which stores a guard area for each task, a holding means 12 which holds the guard area of a task which is being executed, a detecting means 13 which detects that access to the guard area is performed by the task which is being executed, a guard area switching program 112 which sets a guard area after the switching of the task in the holding means 12 when the task is switched, and a guard area registration program 111 which registers the guard area to be set in the guard area chart 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus, and more particularly, to a method for detecting an illegal memory access, a debugging apparatus, and a recording medium.

[0002]

2. Description of the Related Art In the field of embedding a computer, a real-time OS (hereinafter, referred to as an RTOS) is often used for application development due to an increase in application scale and its complexity. The use of the RTOS facilitates design and coding, but makes it very difficult to see the operation of the entire system, and makes it difficult to detect program bugs at the debugging stage. Although a high-performance information processing apparatus is provided with a virtual storage mechanism, it is often not provided with a virtual storage mechanism in this field. For this reason, if a program bug causes illegal access to memory during the execution of a certain task, which may affect other tasks,
Increasingly, it takes a lot of time and effort to determine the cause of the illegal memory access.

For this reason, it is important to easily detect program bugs, to make debugging work more efficient, and to reduce development costs. Conventionally, an in-circuit emulator (hereinafter referred to as ICE) has been used as a debugging device having a mechanism for setting an illegal memory access area as a guard area and detecting an illegal memory access during program execution. However, the conventional technique has the following problems.

[0004]

In an operating system such as an RTOS, there are many situations in which a guard area is different for each task in an execution state, but in the prior art, illegal guard area setting is made independent for each task. And the guard area could not be changed in accordance with the task switching, so that easy and efficient debugging could not be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to set a guard area for each task and dynamically switch the guard area in accordance with the task switching, thereby detecting an easy, efficient and unauthorized memory access. A debugging method, a debugging device, and a recording medium are provided.

[0006]

According to the first method of the present invention, when a task is switched, a guard area, which is a memory area where access is prohibited, is stored for each task when the task is switched. And reading the guard area of the task after switching from the guard area table, and comparing the address of the memory access with the read guard area.

According to a second method for detecting an unauthorized memory access of the present invention, a guard area, which is a memory area for which access is prohibited, is registered and stored in a guard area table when an input request is made by a user. In addition, when a task is switched, a plurality of guard areas of the switched task are read from a guard area table storing a plurality of guard areas for each task, and a memory access address and the read are read. And comparing the plurality of guard areas.

The first debugging device of the present invention comprises a guard area table storing means for registering and storing, for each task, a guard area which is a memory area for which access is prohibited, and a guard area for storing the guard area of the task being executed. The storage unit includes a holding unit that reads from the area table storage unit and holds the same, and a detection unit that detects that the task being executed has accessed the guard area held by the holding unit.

A second debugging apparatus according to the present invention comprises: a guard area table storing means for registering and storing a guard area, which is a memory area whose access is prohibited, for each task; and storing the guard area of the task being executed in the guard area. Holding means for reading and holding from the area table storage means; detecting means for detecting that a task being executed has accessed a guard area held in the holding means; and And setting the guard area after the switching and switching the guard area.

[0010] A third debugging device of the present invention is a guard area table storing means for registering and storing a plurality of guard areas, which are memory areas for which access is prohibited, for each task.
Holding means for reading a guard area of a task being executed from the guard area table storage means and holding a plurality of guard areas; and executing the task accessed at least one of the guard areas held by the holding means. And a procedure for setting the guard area after switching to the holding means and switching the guard area when the task is switched.

A fourth debugging device of the present invention has a shared memory for storing programs and data in addition to the first, second or third debugging device.

According to the recording medium of the present invention, a procedure for registering and storing a guard area, which is a memory area for which access is prohibited at the request of a user, in a guard area table and a procedure for switching between tasks are provided. A program for causing the debug device to execute a procedure of reading the guard area of the task after switching from the guard area table and comparing the address of the memory access with the read guard area to detect an illegal memory access is recorded. .

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 3 is a block diagram of the embodiment. As a form of the debugging apparatus, an in-circuit emulator (ICE) apparatus is shown, and a form in which two guard areas are provided for each task is shown. The ICE device 1 includes a control unit 14 for controlling the ICE device 1, an ICE memory 10, a holding unit 12 for reading and holding a guard area of the task being executed from the guard area table 101, and a memory access address holding unit. A detection unit 13 for detecting whether the area is within the guard area set at 12, an input unit 15, and a display unit 16 are provided. In FIG. 1, the input means 1 is connected to the ICE device 1.
5 and display means 16, which need not be in the ICE device 1, but may be connected to an external device via an interface and input and display may be performed by the external device.

The ICE control program 11 is a program executed on the ICE device 1 and includes a guard area registration program 111 and a guard area switching program 11
2 is also included. The recording medium 2 is a medium that stores these programs, and the stored programs are loaded into the ICE device 1 as needed. The memory 30 is a memory of the device 3 to be debugged. The program 40 executed by the debugged device 3 includes a plurality of tasks. FIG. 1 illustrates only the tasks 41 to 43 for the sake of simplicity, but generally includes several tens or more tasks in general. The task switching means 44 realized by a task dispatcher or the like controls and switches which task to execute next from the tasks 41 to 43.

FIG. 2 is a diagram for explaining the guard area table 101. In FIG. 1, the guard area table 101 is provided in the ICE memory 10, but may be provided in a storage unit different from the ICE memory 10. In particular, when the guard area table is provided in an information processing device other than the debug device, it may be easier to control the guard area table if the guard area table is provided in storage means managed by the firmware.

In the guard area table 101, two entries, a guard area A and a guard area B, are set for each task and registered as many as the number of tasks. In the present embodiment,
Since the number of tasks is three, the task consists of a total of six entries. When the number of tasks is four or more, the entries of the guard area A and the guard area B may be set and added to the guard area table 101 by the number of tasks. Although FIG. 1 shows a case where two guard areas are provided for each task,
When three or more guard areas are provided for each task, the guard area C and the guard area D may be added for each task, and the register of the holding means 12, the comparison circuit and the related circuits of the detection means 13 may be added. It can be added or changed as needed.

As shown in FIG. 3, each entry of the guard area table 101 has a V bit indicating whether the guard area is valid and a lower limit address of the guard area (hereinafter referred to as LLA).
) And an upper limit address (hereinafter, also referred to as ULA). The V bit in the initial state is set to “0”. By determining the size of the designated area of the guard area in advance, the guard area can be represented by only one piece of address information without having both the lower limit address and the upper limit address. For example, if the size of the guard area is defined in units of 1 Mbyte, the lower 20
Only one upper address portion excluding the bits needs to be used for each guard area. In this case, there is an advantage that the circuit and the guard area table are made smaller, but at the same time, there is a disadvantage that the setting of the guard area is more restricted.

FIG. 4 shows the holding means 12 and the detecting means 13 of FIG.
FIG. 3 is a block diagram showing in detail. The holding unit 12 holds a register 121 for holding the guard area A of the task being executed.
And a register 122 for holding the guard area B. Register 121 has V bit, LL of guard area A
A, ULA1, and VLA1 which respectively hold ULA, and ULA1.
Reference numeral 2 includes a V2 portion, an LLA2 portion, and an ULA2 portion that respectively hold the V bit, LLA, and ULA of the guard area B.

Although not shown, the debugged device 3 and the ICE device 1 are connected to each other using an input / output pin of a processor chip of the debugged device 3 as an interface.
The program 40 is executed on the device to be debugged 3. However, when the program 40 is connected to the ICE device 1 to execute debugging, the program 40 is executed under the control of the ICE control program 11 executed on the ICE device 1. Therefore, the memory access executed by the program 40 is sent from the ICE device 1 to the device to be debugged 3 via the memory address line X2, so that the memory address line X2 and the registers 121 and 122
Are compared by the comparison circuit, an illegal memory access can be detected.

In the detecting means 13, the comparison circuit 131
Outputs “1” when the value of the memory address line X2 is larger than the value of LLA of the register 121,
Is based on the value of the memory address line X2,
When the value of LA is large, "1" is output. AND circuit 1
At 35, the logical product of the output of the comparison circuit 131 and the output of the comparison circuit 132 is output, and the memory address is set to the guard area A.
Is detected. However, when the V bit of the register 121 is “0”, the detection becomes invalid. Similarly, the comparison circuit 133, the comparison circuit 134, and the AND circuit 136 are circuits for detecting whether or not the address of the memory access is within the guard area B. The OR circuit 137 outputs the logical sum of the detection results of the guard area A and the guard area B, and notifies the control unit 14 via the detection signal line X4 that the task being executed has accessed the guard area. The memory address line X2 may be a bus for transferring data other than the memory address. The control unit 14 refers to the detection signal line X4 only when a valid memory address is output on the memory address line X2.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings. A user who debugs the debug target device 3 using the ICE device 1 sets a guard area for each task from the input unit 15 before executing the program 40. When the user requests the guard area registration, the ICE control program 11 calls the guard area registration program 111, and the guard area information input by the guard area registration program 111 is stored in the guard area table 101 as an entry shown in FIG. Registered in format. Once the contents of the guard area table 101 registered once are saved, when the debugging is repeatedly performed, the saved guard area table 101 is loaded, so that re-registration can be omitted and efficient debugging can be performed. Can be. Alternatively, if the guard area table is provided in a nonvolatile storage element other than the memory, for example, a flash memory, it becomes easier to use.

As the first guard area for the task 41, the lower limit address = LLA41-1 and the upper limit address = U
The operation of the guard area registration program 111 will be described with reference to FIG. 5 in the case where the LA 41-1 has input the lower limit address = LA 41-2 and the upper limit address = ULA 41-2 as the second guard area. Since the guard area A is input, steps S101 to S102
Then, the execution of step S102 causes the V bit = for the entry 1011 of the guard area table 101 in FIG.
"1", LLA = LLA41-1, ULA = ULA41
-1 is written. Subsequently, since the guard area B is also input, steps S104 to S105 in FIG.
The execution proceeds to step S105, and the V bit for the entry 1012 of the guard area table 101 in FIG.
“1”, LLA = LLA41-2, ULA = ULA41
-2 is written. The above is the case where both the guard area A and the guard area B have been input. If there is no guard area input, the V bit is set to “0” and written to the entry in the guard area table 101.

The user starts the program 40 after performing the above input operation. The program 40 executes processing while switching tasks by the task switching means 44. The ICE control program 11 calls the guard area switching program 112 when detecting that the task switching means 44 has switched the task.
The method of detecting task switching depends on the target instruction set, and may be detected by the ICE control program 11 or notified to the ICE control program 11 by an instruction from the program 40.

Next, a case in which the task is switched to the task 41 and activated will be described.
Operation 2 will be described with reference to the flowchart of FIG.

In step S201, the guard area table 101
The guard area A of the task 41 is read from the entry 1011 of FIG. Since the V bit = “1” is written, steps S204, S205, and S206 are sequentially executed, and “1” is set in the V1 portion of the register 121 of FIG. 4, LLA41-1 is set in the LLA1 portion, and ULA4−1 is set in the ULA1 portion. 1
Is set. Subsequently, steps S211, S212, S
Steps 214, S215, and S216 are sequentially performed. The guard area B of the task 41 is read from the entry 1012 of the guard area table 101, “1” is written in the V2 part of the register 122 in FIG. 4, LLA41-2 is written in the LLA2 part, and ULA is written in the LLA2 part.
ULA41-2 is set in the A2 portion.

When the guard area is set in the holding means 12 by the guard area switching program 112 in this way, the detecting means 13 compares the address on the memory address line X2 with the guard area A and the guard area B. When the guard area A or the guard area B is accessed, a detection signal is output to the detection signal line X4. When the detection signal is notified, if the address on the memory address line X2 is currently valid, the control unit 14 determines that the access to the guard area has been executed, and notifies the ICE control program 11. Upon receiving this notification, the ICE control program 11 temporarily stops the processing being executed. After that, the operation shifts to the user's operation environment for the user to obtain valid information, or the predetermined information on the information of the stopped state is recorded in the ICE memory 10 and the processing is further continued. Or will be. When the operation environment has been shifted to the user's operation environment,
The desired information can be collected by using the debugging means provided in the program. The operation after detection can be selected by the user in accordance with the purpose of debugging, and efficient debugging can be performed.

[0027]

As described above, according to the present invention, there is provided a means for dynamically changing and setting the guard area set for each task in accordance with the task switching of the RTOS. There is an effect that an illegal memory access for each task can be easily detected. By providing two or more guard areas, more complicated debugging can be easily performed. Further, since the detection means and the holding means only need to be provided for the number of guard areas in task units, the hardware amount can be kept as it is even if the number of tasks increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a guard area table 101 according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an entry format of a guard area according to the embodiment of the present invention.

FIG. 4 is a block diagram of a holding unit 12 and a detecting unit 13 according to the embodiment of the present invention.

FIG. 5 is a flowchart of a guard area registration program 111 according to the embodiment of the present invention.

FIG. 6 is a flowchart of a guard area switching program 112 according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ICE apparatus 2 Recording medium 3 Device to be debugged 10 ICE memory 101 Guard area table 11 ICE control program 111 Guard area registration program 112 Guard area switching program 12 Holding means 121 Register 122 Register 13 Detection means 131 Comparison circuit 132 Comparison circuit 133 Comparison circuit 134 comparison circuit 14 control unit 15 input means 16 display means 30 memory 40 program

Claims (7)

[Claims] In a method for detecting an illegal memory access in a debugging device connected to a processing device that executes while switching a plurality of tasks, when a task is switched, a guard area which is a memory area whose access is prohibited when the task is switched. A method of reading a guard area of a task after switching from a guard area table storing for each task, and comparing an address of a memory access with the read guard area to detect an illegal memory access. 2. A method for detecting an illegal memory access in a debugging device connected to a processing device which executes a plurality of tasks while switching between the tasks, comprising the steps of: A certain guard area is registered and stored in a guard area table, and when a task is switched, a plurality of guard areas of the task after switching from a guard area table storing a plurality of guard areas for each task are stored. A method for detecting an illegal memory access by reading an area and comparing a memory access address with the plurality of read guard areas. 3. A guard area table storing means for registering and storing, for each task, a guard area, which is a memory area for which access is prohibited, in a debugging apparatus which is used by being connected to a processing apparatus which executes while switching a plurality of tasks. Holding means for reading and holding the guard area of the task being executed from the guard area table storage means, and detecting means for detecting that the task being executed has accessed the guard area held in the holding means. Debugging device with 4. A guard area table storage means for registering and storing, for each task, a guard area, which is a memory area for which access is prohibited, in a debugging apparatus connected to a processing apparatus which executes a plurality of tasks while switching the tasks. Holding means for reading and holding the guard area of the task being executed from the guard area table storage means, and detecting means for detecting that the task being executed has accessed the guard area held in the holding means. A debugging apparatus characterized in that when a task is switched, a guard area after switching is set in the holding means and the guard area is switched. 5. A guard area table for registering and storing a plurality of guard areas, each of which is a memory area for which access is prohibited, for each task in a debugging apparatus connected to a processing apparatus for executing a plurality of tasks while switching the tasks. Storage means, holding means for reading a guard area of a task being executed from the guard area table storage means and holding a plurality of guard areas, and at least one of a plurality of guard areas in which the task being executed is held in the holding means Detecting means for detecting access to one of the devices, wherein when the task is switched, the guard area after switching is set in the holding means and the guard area is switched. 6. The debugging device according to claim 3, further comprising a shared memory for storing programs and data, wherein said guard area table storage means is provided in said shared memory. Debugging device. 7. A procedure for registering and storing a guard area, which is a memory area for which access is prohibited, in a guard area table when an input request is made by a user, and a procedure for storing the guard area when a task is switched. Reading a plurality of guard areas of the switched task from a guard area table storing a plurality of areas for each task, and comparing a memory access address with the read plurality of guard areas. A recording medium on which a program to be executed by a debugging device is recorded.