JPS63150732A - Program running supervisory equipment - Google Patents

Abstract

PURPOSE:To prevent destruction of a program or a data due to program runaway in advance by detecting the runaway of the program due to deviation of stack and combining the result with a program running supervisory equipment. CONSTITUTION:An instruction decode circuit supervises the execution of stack save register restoration instruction or subroutine restoration instruction. When the instruction is generated, the CPU reads the save register or return address from the stack memory M3. Moreover, a flag read circuit reads a flag of the flag memory M4 and effective flag and sends the flag check circuit FC. The circuit FC discriminates an identification flag while the effective flag is set to check whether or not the level is '1'. When '1', the effective flag is reset and if '0', it is judged to be program runaway. Then the signal line l4 is made active to cause alarm. When the read effective flag is reset, alarm is raised.

Description

[Detailed Description of the Invention] [Summary] A circuit is provided that stores a flag that identifies whether the contents saved to the stack area are a subroutine return address or a save register, and the flag is set at the time of save and checked when the stack contents are restored. This allows for detection of runaway behavior.

[Industrial application field]

The present invention makes it possible to detect program runaway that occurs when a subroutine is returned without restoring registers after saving registers in a processing device equipped with a CPU that saves subroutine return addresses and saves registers using a stack method. The present invention relates to a program running monitoring device.

Program runaways in CPU-equipped devices as described above often occur during the software debugging process, and it is important to quickly grasp the situation, prevent data destruction due to runaways, and reduce the debugging process. It is.

[Conventional technology]

As is well known, the central processing unit (CPU) has, for example, 16
Bit index register (X-Reg), 8-bit A register, B register (A-Reg).

B-Reg), and an instruction register (IR-Reg). An instruction having a function part and an operand part is set in the I R-Reg, and the function part is decoded by a decoder to determine whether the instruction is a memory read instruction, a write instruction, etc. The operand section is for calculation/addressing. The CPU also includes a memory, and this memory has a program area, a data area, a stack area, and the like.

The stack area saves the contents of registers and also stores the return address when a subroutine is called.

The program jumps from main routine to subroutine,
It is executed while going through processes such as returning to the main routine, but when jumping to a subroutine ■X, A, B...
...Stores the contents of Reg in the stack area, then ■Jumps to the subroutine with a jump command, ■Executes the subroutine, and returns to the main routine again with the return command at the end of the execution. The register contents saved in the stack area are restored to each register, and the next and subsequent steps of the main routine are executed. Now, if the above ■ is address n-1 and ■ is address n, the address of the main routine returned by the return instruction is n+1, so when executing ■ above, this fi
Store +l in the stack area as a return address.

A pointer indicating an address to access the stack area is provided. Initially, the pointer is O, and data is stored in X-Reg and A.

If this is done in the order of B-Reg s return address, the pointer will be incremented by 1 every time this data is stored.
Therefore, the contents of X-Reg are address 1, A, B-
The contents of Reg are stored in address 2, and the return address is stored in address 3. When executing the return instruction, the address of the stack area indicated by the pointer is read, thereby obtaining the above n+1, which is set in the program counter, and the main routine from address n+1 onward is executed. The pointer increases by 1 each time it is written.
It is decremented by 1 each time it is read, so when the return address is read, the contents of A and B-Reg are next, and then the contents of X-R
The contents of eg are read and returned to their respective registers.

[Problem that the invention seeks to solve]

If the register contents and return address are saved correctly to the stack area, the return address can be obtained by executing the return instruction, and the register contents can be restored. However, if this is not done correctly, For example, if the above evacuation is not completed, the pointer will be 0.
, and when the return instruction is executed, the O address of the stack area is read. Of course, this does not contain a return address, and a normal return to the main routine is not performed, resulting in a program runaway.

Also, registers may be saved in the subroutine, but if the registers are not restored before returning to the main routine, the pointer will not point to the address in the stack area that stores the return address. In such a case, the program will run out of control.

Conventional program runaway detection methods include methods that do this by detecting invalid addresses, and methods that issue an alarm if a certain address is not accessed within a certain period of time. In other words, since the program area, data area, etc. of the memory are between the predetermined start address and end address, these are checked, and if the read return address is not within the program area, it is judged as an abnormality (invalid address). This is the former method. The latter uses a certain area of memory as a counter, sequentially increments it by 1 using the clock, and the CPU clears it periodically.
In this system (watched timer or timer overflow counter system), if the return address is abnormal and a program runaway occurs, the above-mentioned clearing is not performed, the counter overflows, and an alarm is generated due to this overflow.

However, with these conventional methods, if the contents of the save register become the subroutine return address due to a shift in the stack level due to forgetting to restore a register, etc., an abnormality cannot be detected if the return address is within the address range of the regular program. There are drawbacks.

The present invention aims to improve these points and provide a system that can reliably detect program runaway due to stack pointer shift.

Means for Solving Problem C] The present invention provides a central processing unit (CP
In a processing device equipped with U), an instruction decoding circuit, a circuit (SCI, 5C3) that generates a flag to identify whether the contents saved in the stack area are a subroutine return address or register contents, and a memory in which the flag is written ( M4) and a circuit for reading out the identification flag of the memory (
FR) and a circuit for checking the read flag (F
C'), and is characterized in that an alarm is generated when the decoding result of the instruction decoding circuit indicates a return instruction and the check result of the flag check circuit (FC) indicates that it is not a subroutine return address. It is.

[Effect]

According to this method, it is possible to detect program runaway due to stack misalignment, and by combining this with a conventional program run monitoring device, more complete program run monitoring can be performed. Data destruction can be prevented.

〔Example〕

FIG. 1 shows an embodiment of the present invention. The central processing unit CPU is connected to a program memory M + and a data memory M 3 via an address bus AB and a data bus DB.

and a stack memory M3, and sequentially fetches and executes instructions from the program memory M1, and reads from or writes to the data memory M2 and the stack memory M3. These memo 'JM+~M3 and flag memory M4 are generally not separate memories but one
each area of memory. The instruction decode circuit DEC receives the data bus D by the instruction fetch signal SI from the CPU.
An instruction is received from Ba, decoded, and when the instruction is to save a register, signal line 1+ is activated, and at the same time the CPU writes the contents of the save register to stack memory M3, the ``O'' setting circuit SC+ and valid flag setting circuit SC2 activate the signal line 1+. , writes the identification flag "0" to the address corresponding to the stack memory M3 in the flag memory M4 and sets the valid flag.Furthermore, at the time of an instruction to save the subroutine return address, the signal line j22 is activated and the CPU
writes the subroutine return address in the stack memory M3, and at the same time, the stack memory M in the flag memory M4 is written by the °1° setting circuit SCI and the valid flag setting circuit SC2.
Write the identification flag °1' to the address corresponding to 3 and set the valid flag. When writing the register contents to the stack memory, write the ``0'' flag to the flag memory, and when writing the return address to the stack memory, write the ``1'' flag to the flag memory. A valid flag is set in the identification flag.

The instruction decode circuit DEC monitors when the CPU executes a stack save register restore instruction or a subroutine return instruction, and when this instruction is generated, activates the signal line 13 so that the CPU can restore the save register value or restore ( At the same time as reading the M address, the flag reading circuit FR reads the identification flag and valid flag of the address corresponding to the stack memory M3 in the flag memory M4 and sends them to the flag checking circuit FC.In addition, the instruction decoding circuit DEC decodes the instruction. If the result is a subroutine return command, a pulse is sent to the flag check circuit FC via the timing pulse generator TP'G to cause the flag check to be performed.The circuit FC determines the identification flag while the valid flag is set. Then, in this example, it is checked whether the content corresponds to the generated instruction or not. In this example, it is checked whether it is "1".
When the valid flag is reset and the response is not taken (
If the value is "0", it is determined that the program has runaway, and the signal line 14 is activated to generate an alarm.Also, if the read valid flag has been reset, an alarm is generated.

FIG. 2 is an explanatory diagram of the above operation. Main routine MA
When IN enters the jump section to the subroutine SUB, register saving is first performed, and in this example, this is performed in the order of the X, A, and B registers. The stack pointer is initially 0
If it is pointing to X.

The contents of registers A and B are sequentially stored in addresses 1, 2, and 3 of stack memory M3 (here, each register is 2 bytes). At this time, the instruction is decoded by the instruction decode circuit, and the instruction is saved to the register (store ST).
), the “0” setting path is activated and the flag memory M4 is
Same address 1. 2. 3 is sequentially written with 0.

Note that a valid flag is also written, but is not shown here.

Next, the jump commands J and SUB to the subroutine are issued, and the jump to the subroutine is made. However, when J and SUB are decoded, the instruction decode circuit drives the "1' stage setting path, and the address 4 of the flag memory M4 is set to "1". is written. Further, the hardware generates a return address n+1, which is written to address 4 of the stack memory M3.

When a subroutine is executed, a register save instruction STX may also be included, and when this occurs, the contents of the X register are saved to address 5 of M3, and O is written to the same address of M4.

If normal, register recovery command LS is executed within the same subroutine.
TX is included, and when this is executed, address 5 of M3 is read out and loaded into register X, and M3.
The pointer of M4 is also incremented by 1 and now points to address 4.

The floor of the subroutine contains a return instruction RT, and when this is executed, address 4 of memory M3 is read and return address n+1 is taken out. At this time, address 4 of memory M4 is also read and flag l is taken out. In addition, the instruction decode circuit decodes the instruction, and if it is a return instruction, in this example, the °1" setting circuit is activated and outputs "1". This 1 and the above flag 1 are exclusive ORed, and the If they match, a normal OK output is output. If they do not match, it is abnormal and an alarm is issued. When register recovery occurs, in this example, the "0" setting path is driven and "0" is output. , if the flag read from the flag memory is also normal, it is 0, and the result of exclusive OR is 0, normal.

〔Effect of the invention〕

As explained above, according to the present invention, runaway of a program due to stack misalignment can be detected, and by combining this with a conventional program run monitoring device, more complete program run monitoring can be performed. , it is possible to prevent program or data destruction due to program runaway.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of FIG. 1.

Claims (1)

[Scope of Claim] A processing device equipped with a central processing unit (CPU) that saves the return address of a subroutine and saves registers using a stack method, comprising: an instruction decoding circuit, and whether the contents saved in the stack area are the subroutine return address or the contents of the registers. A circuit that generates a flag to identify whether
SC_1, SC_3), a memory (M_4) into which the flags are written, a circuit (FR) for reading the identification flag of the memory, and a circuit (FC) for checking the read flag, and decoding with an instruction decoding circuit. A program run monitoring device characterized in that an alarm is generated when the result is a return instruction and the check result of the flag check circuit (FC) indicates that it is not a subroutine return address.