JPH02103639A - Microprogram error correction circuit - Google Patents

Abstract

PURPOSE:To correct an error by generating an enable signal so that the output value of the 1st register can be outputted onto a data bus upon detecting the error and setting proper data on the data bus in the 2nd register. CONSTITUTION:An error detection circuit 8 checks the coincidence between a check bit signal (b) and comparison bit signal (c) and when a checked result of the circuit 8 is discordant and at the same time, the RD error signal (a) of a microprogram readout register (RD) 2 indicates no error, namely, when the error of an RD 5 is detected, an enable signal is outputted so that the output data of the RD 2 can be outputted to a controlling storage device (CS) bus 9. The RD 5 sets proper microprogram data in the RD 2 from the CS bus 9 at the next clock. Therefore, an error in a microprogram can be corrected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram error correction circuit in an information processing device, and in particular, error detection when microprogram read registers are present in multiple locations. It concerns the correction method.

[Conventional technology]

Conventionally, this type of error correction circuit has a first register that holds all of the microprogram data and error detection data read from the control storage device, and a second register that holds only some bits. A check bit generation circuit generates a check bit from the output value of the second register, and a comparison bit is generated from the bit held in the second register out of the output of the first register using the same logic as the check bit generation circuit. It has a comparison bit generation circuit that checks whether the check bit and the comparison bit match, and performs error detection.

[Problem to be solved by the invention]

The conventional microprogram error correction circuit described above can detect errors in registers that do not hold error detection data in the multiple microprogram read registers, but cannot correct errors, even if they are intermittent failures. The problem is that if this occurs, the system will stop.

[Means for Solving the Problems] In order to eliminate such drawbacks, the microprogram error correction circuit according to the present invention includes a control memory device having error detection data and bidirectional input/output pins, and a control memory device having bidirectional input/output pins. a first register that holds all bits of microprogram data and error detection data read from the device; an error check circuit that performs an error check using the microprogram data and error detection data in the first register; A second register that holds only some bits of the microprogram data that does not include read error detection data, a control storage device, inputs and outputs of the first register, and inputs of the second register are configured in a bus configuration. A check bit generation circuit that generates a check bit from the connected data path and the output value of the second register, and a check bit generation circuit that uses the bit held in the second register from the output value of the first register. A comparison bit generation circuit that generates a comparison bit with the same logic as , checks the output value of the check bit generation circuit and the output value of the comparison bit generation circuit, and if there is a mismatch, the error check circuit writes the output value to the first register. An error detection circuit is provided which detects the data in the second register as an error when no error has occurred.

[Effect]

The error detection circuit of the microprogram error correction circuit according to the present invention has a check bit generated from the output value of a register that only has a part of the focus, and a comparison bit generated from the output value of the register that holds all the bits. When the microprogram data of the register holding all bits and the error detection data do not match and there is no error in the error check, the data of the register holding only some bits is determined to be an error.

When the above error is detected, the error is corrected by outputting the data in the register holding all bits onto the data path and setting it in the register holding only some bits.

〔Example〕

FIG. 1 is a system diagram showing an embodiment of a microprogram error correction circuit according to the present invention. In the figure, reference numeral 1 denotes a control storage device (C3) that holds a microprogram including ECC data (error detection data), and is composed of a RAM that uses a common data line for reading and writing. 2 is a 64-bit microprogram read register (RD); 3 is an ECC register that holds 8-bit ECC data read from the control storage device 1 along with the microprogram; 4 is a 64-bit microprogram read register (RD); 4 is a 64-bit microprogram read register (RD); An error check circuit performs an error check using an output value and generates an RD error signal a, and 5 is a microprogram read register. The microprogram read register 5 does not have all the bits read from the control storage 1;
Some bits (e.g. 3 from bit 0 to bit 31)
2 bits). 6 is a check bit generation circuit that calculates the exclusive OR of the 32-bit output data of the microprogram read register 5, and 7 is the bit 0 to bit 31 of the output data of the microprogram read register 2.
8 is an error detection circuit that detects an error in the microprogram read register 5. A CS bus 9 serves as a data path that connects the microprogram read register 2, the ECC register 3, and the control storage device 1, and is connected only to the input of the microprogram read register 5.

All 6 microprograms read from control storage device 1
4 bits and 8 bits of ECC are microprogram read register 2. At the same time as being set in ECC register 3, bits 0 to 31 of the microprogram data
The up to 32 bits are also set in the microprogram continuation register 5.

The output data of the microprogram read register 5 is input to the check bit generation circuit 6, where a 32-bit exclusive OR is generated and combined into a 1-bit signal.
The signal is input to the error detection circuit 8.

On the other hand, among the output data of the microprogram read register 2, bits 0 to 31, which are the same bits as the bits held in the microprogram read register 5, are input to the comparison bit generation circuit 7, and like the check bit generation circuit 6, 32 bits are input. The exclusive OR is performed to generate a 1-bit signal C, which is input to the error detection circuit 8.

Also, microprogram read register 2 and EC
All bits of the C register 3 are input to an error check circuit 4, the entire microprogram read register 2 is checked for errors, and an RD error signal indicating the presence or absence of an error is input to an error detection circuit 8.

The error detection circuit 8 checks whether the check bit signal C and the comparison bit signal C match, and when the result is a mismatch and indicates that there is no error in the RD error signal of the microprogram read register 2, that is, the microprogram read register 2 5 error is detected, the output data of microprogram read register 2 is sent to CS.
An enable signal is output to output to bus 9.

The microprogram continuation register 5 reads the correct microprogram from the CS bus 9 at the next clock and sets the microprogram data in the register 2.

〔Effect of the invention〕

As explained above, the present invention provides a data pass when the data in the microprogram read register that holds all bits is correct and an error occurs only in the register that holds only some bits. By sending correct data between the microprogram read registers connected via a bus, errors can be corrected.

[Brief explanation of the drawing]

The figure is a system diagram showing a microprogram error correction circuit according to the present invention. 1... Control storage device, 2.5... Microprogram read register, 3... ECC register, 4...
Error check circuit, 6... Check bit generation circuit, 7... Comparison pit generation circuit, 8... Error detection circuit, 9... CS bus.

Claims (1)

[Claims] a control storage device having error detection data and bidirectional input/output pins; a first register holding all bits of microprogram data and error detection data read from the control storage device; an error check circuit that performs an error check using microprogram data and error detection data; a second register that holds only some bits of the microprogram data that do not include the error detection data read from the control storage device; a data path connecting a storage device, the input and output of the first register, and the input of the second register in a bus configuration; a check bit generation circuit that generates a check bit from an output value of the second register; A comparison bit generation circuit that generates a comparison bit using the same logic as the check bit generation circuit using the bit held in the second register out of the output value of the first register, and a comparison bit generation circuit that uses the output value of the check bit generation circuit and the comparison bit generation circuit. and an error detection circuit that performs a match check with the output value of the circuit, and determines that the data in the second register is an error if there is a mismatch and an error check circuit indicates that no error has occurred in the first register. The circuit generates an enable signal to output the output value of a first register onto the data path upon detection of an error, and a second register sets correct data on the data path. Program error correction circuit.