JPH04329444A - Error correcting and detecting system for information processor - Google Patents

Abstract

PURPOSE:To correct one-block error generated in transfer between a host device, which reads/writes data, and a storage device and to reduce an entire hardware amount. CONSTITUTION:A check bit generating circuit 11-2 to generate a check bit from written data and to add it to the written data and an error correcting and detecting circuit 11-4 to check read data and the check bit and to correct or detect them are housed in a host device 11, and a parity generating circuit for data transfer and a parity check circuit between the host device 11 and a storage device 12 are excluded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an information processing device,
In particular, the present invention relates to an error correction detection method for an information processing device having a storage device and a host device.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 2, an error correction detection method for this type of information processing apparatus accommodates a check bit generation circuit 22-3 and an error correction detection circuit 22-4 in a storage device 22. , Also, the host device 21 and the storage device 2
Parity generation circuits 21-2 and 22- for performing parity check of write and read data transferred between
5 and parity check circuits 21-4 and 22-2.

Next, the operation will be explained. During writing, the parity generation circuit 21-2 receives the write data output from the write data output circuit 21-1 in the host device 21.
The parity generated in is added and transferred to the storage device 22,
Parity check circuit 22-2 in storage control unit 22-1
At the same time, the check bit generating circuit 22-3 generates a check bit and stores it in the storage unit 2.
Write data and check bits to 2-6.

During reading, the error correction and detection circuit 22-4 in the storage control unit corrects or detects errors in the read data based on the data read from the storage unit 22-6 and check bits, and parity is added to the corrected read data. The parity generated by the generation circuit 22-5 is added and sent to the host device 21, inputted to the read data input circuit 21-3, and a parity check is performed by the parity check circuit 21-4.

[0005]

[Problem to be Solved by the Invention] However, in this conventional error correction detection method, the transfer between the host device 21 and the storage device 22 only performs a parity check, and one block error occurs during this time. if you did this,
There was a problem in that the data was not corrected and if it occurred again after a retry, the system would go down.

The present invention was made in view of the above-mentioned problems, and provides an error correction detection method for an information processing device that makes it possible to correct a single block error that occurs during transfer between a host device and a storage device. For the purpose of providing.

[0007]

[Means for Solving the Problems] In order to achieve the above object, an error correction detection method for an information processing device according to the present invention is provided in an information processing device having a storage device and a host device that reads and writes data to the storage device. , the host device includes a write data output circuit that outputs data to be written to the storage device, a check bit generation circuit that generates a check bit from the write data from the write data output circuit and adds it to the write data, and a check bit generation circuit that outputs the data to be written to the storage device. The configuration includes a read data input circuit that inputs read data that has been read, and an error correction detection circuit that corrects or detects errors by checking the read data and check bits input by the read data input circuit.

[0008]

[Operation] According to the error correction detection method for an information processing device having the above configuration, a check bit generation circuit that generates a check bit to be added to write data is included in the host device, and an error correction detection circuit that performs error correction or detection of read data. Since the circuit is accommodated, it becomes possible to correct a one-block error that occurs during transfer between the host device and the storage device.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention.

In the figure, 11 is a host device that writes and reads data to and from the storage device 12; 11-1 is a write data output circuit that outputs data to be written to the storage device 12;
11-2 is a check bit generation circuit that generates a check bit from the write data, adds it to the write data, and sends it to the storage device 12; 11-3 is a read data input circuit that inputs the data read from the storage device 12; -4
is an error correction and detection circuit that checks the data and check bits read from the storage device 12 and corrects or detects errors.

12 is a storage device that stores data written and read from the host device 11; 12-1 is a storage control unit that accesses a predetermined address of the storage unit 12-2 to write or read data; 12-2 is a storage unit that stores and holds data written and read from the storage control unit 12-1 at a predetermined address.

Therefore, in this embodiment, during writing, the check bit generated by the check bit generation circuit 11-2 in the host device 11 is added to the write data output from the write data output circuit 11-1 in the host device 11. is added and transferred to the storage device 12, and data and check bits are written to a predetermined address in the storage section 12-2 according to a control signal generated in the storage control section 12-1.

The host device 11 and the storage device 12 are not provided with a parity generation circuit and a parity check circuit, respectively, and parity generation and checking are not performed during data and check bit transfer between the host device 11 and the storage device 12. do not have.

On the other hand, during reading, the data and check bits read from the storage section 12-2 are transferred to the storage control section 1.
2-1, the read data and the check bit are checked by the error correction detection circuit 11-4 in the host device 11, and the error is corrected or detected, and the read data is input. Input to circuit 11-3.

As in the case of writing, a parity generation circuit and a parity check circuit are not provided in the storage device 12 and the host device 11, respectively, and parity is used in data and check bit transfer between the storage device 12 and the host device 11. is not generated or checked.

[0016]

As explained above, according to the error correction detection method of the information processing device of the present invention, the check bit generation circuit and the error correction detection circuit are housed in the host device, so that the host device and the storage device can be easily connected to each other. It is possible to correct a one-block error that occurs during transfer, and even if it is a fixed failure, the system can continue to operate while correcting data until repairs are made without bringing the system down.

Furthermore, since the parity generation circuit and the parity check circuit for performing parity check of write/read data transferred between the host device and the storage device are eliminated, the overall amount of hardware can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an error correction detection method of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an error correction detection method of a conventional information processing device.

[Explanation of symbols]

11 Upper device 11-1 Write data output circuit 11-2 Check bit generation circuit 11-3 Read data input circuit 11-4 Error correction detection circuit 12 Storage device 12-1 Memory control unit 12-2 Storage section 21 Upper device 21-1 Write data output circuit 21-2 Parity generation circuit 21-3 Read data input circuit 21-4 Parity check circuit 22 Storage device 22-1 Memory control unit 22-2 Parity check circuit 22-3 Check bit generation circuit 22-4 Error correction detection circuit 22-5 Parity generation circuit 22-6 Memory section

Claims (1)

[Claims] Claim 1. An information processing device comprising a storage device and a host device that reads and writes data to the storage device, wherein the host device includes a write data output circuit that outputs data to be written to the storage device, and a write data output circuit that outputs data to be written to the storage device. A check bit generation circuit that generates a check bit from write data from a circuit and adds it to the write data, a read data input circuit that inputs read data read from a storage device, and a read input circuit that inputs the read data input circuit. 1. An error correction and detection method for an information processing device, comprising an error correction and detection circuit that corrects or detects errors by checking data and check bits.