JPH03288935A - Error correcting device for information processor - Google Patents

Abstract

PURPOSE:To prevent data from being changed due to the fault in an error correcting circuit part and to improve the reliability of this device by adding a parity bit corresponding to the data from the data before the error correction of data. CONSTITUTION:The device is equipped with a syndrome generation circuit 1, correcting spot detection circuit 2, parity generation circuit 3, data correction circuit 4, parity correcting spot detection circuit 5 and parity correction circuit 6. In the case of executing the error correction of data in an information processing, the parity bit corresponding to the data is generated before correcting the error of the data and when the data is corrected, the generated parity bit is corrected. Thus, the data is prevented from being changed by the fault of the error correction circuit part or the like and the reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to information processing devices and digital communication devices. The present invention relates to an error correction device that detects data errors and corrects them.

〔overview〕

The present invention provides an error correction device for correcting data errors in information processing, which generates parity bits corresponding to the data before correcting data errors, and when the data is corrected, the generated parity bits are By correcting the data, data is prevented from changing due to failure of the error correction circuit, and reliability is increased.

[Conventional technology]

Conventionally, this type of error correction device decodes received data and error correction check bits, corrects the received data depending on the presence or absence of errors, and sends it as output data to a host device, but the parity of the output data at this time The bits were generated and added from the corrected data.

[Problems to be Solved by the Invention] The conventional error correction device described above generates the parity bit added to the output data from the error-corrected data, so if an error is incorrectly corrected due to a malfunction, etc. This method has the disadvantage that the error cannot be detected and data different from the required data is output, reducing reliability.

The present invention aims to eliminate such drawbacks, and aims to provide a device that can prevent data from being changed due to failure of the error correction circuit.

[Means to solve the problem]

The present invention provides an error correction device for an information processing device that is equipped with a data correction means that receives a data signal and a corresponding error correction check bit signal, corrects the corresponding data, and outputs the corrected data. The present invention is characterized by comprising a parity generation circuit that generates bits, and a parity correction means that corrects the parity signal generated by the parity generation circuit according to the number of data corrected by the data correction means.

The data correction means includes a syndrome generation circuit that generates a syndrome from the received data, and a correction point detection circuit that detects whether or not there is a correction point based on the syndrome and outputs a correction signal if there is a correction point. , a data correction circuit that corrects received data based on a data signal and a correction signal from the correction point detection circuit, and the parity correction means searches for a correction point of the parity bit based on the output of the correction point detection circuit. and a parity correction circuit that outputs a parity signal corrected in accordance with the parity signal from the parity generation circuit and the parity correction signal from the parity correction point detection circuit. be able to.

[Effect]

Generates parity bits corresponding to data before error correction, then checks data errors, corrects data and its parity bits if correction is required, and sends out error correction data signals and corresponding data parity signals. .

In other words, a parity bit is generated from the data before data correction, and this parity bit is corrected when the data is corrected. Therefore, if there is a failure in the data correction circuit, an error will occur in the parity bit sent out and the subsequent stage (or host device) can notice the failure.

This prevents data from changing due to a failure of the error correction circuit, and improves the reliability of the device.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes data correction means for receiving a data signal group 10 and a corresponding error correction check bit signal group 11, correcting the corresponding data, and outputting the corrected data. a parity generation circuit 3 that generates parity bits that pass through, and a parity correction means that corrects the parity signal group 12 generated by the parity generation circuit 3 according to the number of data corrected by the data correction means, and the data correction means includes a syndrome generation circuit 1 that generates a syndrome group 13 from received data, and a syndrome generation circuit 1 that detects whether or not there is a correction point from the syndrome group 13, and if there is a correction point, a correction signal group 14.
and a data correction circuit 4 that corrects the received data based on the data signal group ■0 and the correction signal group 14 from the correction point detection circuit 2, and the parity correction means includes a a parity correction location detection circuit 5 that searches for a correction location of the parity bit based on the output of the location detection circuit 2 and outputs a parity correction signal group ■5;
Parity signal group 12 from parity generation circuit 3 and parity correction signal group 1 from parity correction point detection circuit 5
5, the parity correction circuit 6 corrects the parity signal group 12 generated by the parity generation circuit 3 corrected according to No. 5.

The embodiment of the present invention configured in this manner is applied to an error correction and detection circuit for read data of a main memory device (not shown).

The syndrome generation circuit 1 receives the data signal group 10 and the error correction check bit signal group 12 and outputs the syndrome group 13. The correction point detection circuit 2 searches for error points from the received syndrome group 13 and outputs a correction signal group 14. Parity generation circuit 3 receives data signal group 10, generates parity bits, and outputs parity signal group 12.

The data correction circuit 4 receives the data signal group 10 and, if the correction signal group 14 indicates a location to be corrected, corrects the corresponding data and outputs the read data signal group 17. The parity correction location detection circuit 5 detects the number of corrected data from the correction signal group 14, searches for the correction location of the parity bit based on this, and outputs the parity correction signal group 15. Parity correction circuit 6 receives parity signal group 12 and parity correction signal group 15 and outputs read data parity signal group 16.

Next, the operation of the embodiment of the present invention will be explained.

When the syndrome generating circuit 1 receives the data signal group IO and the corresponding error correction check bit signal group 11, the syndrome generating circuit 1 generates a syndrome group 13 using these signal groups and outputs it to the correction point detecting circuit 2. The correction point detection circuit 2 receives the syndrome group 13, checks whether there is an error, and if there is an error and the error can be corrected, outputs a correction signal group 14 instructing correction.

At this time, if there is no correctable error, the data signal group 10 is input to the data correction circuit 4 and is transferred as it is to a host device (not shown) as a read data signal group 17.

Further, the parity generation circuit 3 receives the data signal group 10, generates parity bits, and outputs the harrity signal group 12, but the parity correction circuit 6 transfers it as it is to the host device as the read data parity signal group 16.

If there is a correctable error, the data signal group 10 input to the data correction circuit 4 is corrected by the correction signal group 14 and transferred to the host device as the read data signal group 17. The parity correction point detection circuit 5 has a correction signal group 14
When it is detected that the data has been corrected and the parity bit also needs to be corrected, the parity correction signal group 1
5 to the parity correction circuit 6, and the parity correction circuit 6
corrects the parity signal group 12 with the parity correction signal group 15 and transfers the read data parity signal group 16 to the host device.

By adding a parity bit before correcting data in this way, even if a failure occurs in the data correction circuit 4, the parity bit corresponding to the data will not match, and the failure will therefore be detected by the host device. Furthermore, when a correctable error occurs and the data is corrected, the corresponding parity bit is also corrected if necessary, and the parity bits can always be in a consistent state.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a parity bit corresponding to the data before error correction of the data, changes in data due to failure of the error correction circuit are prevented and reliability of the device is improved. There are effects that can be enhanced.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Syndrome generation circuit, 2... Correction point detection circuit, 3... Parity generation circuit, 4... Data correction circuit, 5... Parity correction point detection circuit, 6... Parity correction circuit , 10... data signal group, 11...
Error correction check bit signal group, 12... Parity signal group, 13... Syndrome group, 14... Correction signal group, 15... Parity correction signal group, 16... Read data parity signal group, 17--Read data signal group.

Claims (1)

[Scope of Claims] 1. In an error correction device of an information processing device that is equipped with data correction means that receives a data signal and a corresponding check bit signal for error correction, corrects the corresponding data, and outputs the data signal transmitted and received. a parity generation circuit that generates a parity bit corresponding to the parity bit, and a parity generation circuit that generates a parity bit corresponding to
An error correction device for an information processing device, comprising: parity correction means for correcting a parity signal generated by the parity generation circuit. 2. The data correction means includes a syndrome generation circuit that generates a syndrome from the received data, and detects whether or not there is a correction part from the syndrome,
2. The information processing according to claim 1, comprising: a correction point detection circuit that outputs a correction signal when there is a correction point; and a data correction circuit that corrects received data based on a data signal and a correction signal from the correction point detection circuit. Equipment error correction device. 3. The parity correction means includes a parity correction part detection circuit that searches for a correction part of the parity bit based on the output of the correction part detection circuit and outputs a parity correction signal; 3. The error correction device for an information processing apparatus according to claim 2, further comprising a parity correction circuit that outputs a parity signal corrected in accordance with a parity correction signal from the parity correction point detection circuit.