JP2600021B2 - Time slot indication check processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot instruction check processing method, and more particularly to a time slot instruction check processing method capable of promptly checking the validity of time slot control.

2. Description of the Related Art In recent years, a communication control processor (CCP) is required to respond to a failure promptly and surely by assuming all causes of a failure in accordance with a demand for a nonstop system. Therefore, it is necessary to detect faults promptly and reliably.

[0003]

2. Description of the Related Art One of the failures in CCP is the destruction of transmitted / received data due to abnormal time slot control. Conventionally, this failure has been detected by a parity check method. FIG. 4 shows a failure detection by the conventional parity check method.

In FIG. 4, a line address register 1
0 consists of registers corresponding to each time slot.
The MPU 6 (and software) sets the line address used in each time slot and its parity in the line address register unit 10. The line address multiplexer unit 11 switches and outputs the line address and its parity output from the line address register unit 10 based on the time slot number.

The line address decoder 12 decodes the output line address and outputs the result. That is, one line is selected. The serial-parallel converter 13 is provided corresponding to each line, and the serial-parallel converter 13 corresponding to the line of the selected address is:
Performs serial-parallel conversion of transmission / reception data. That is,
The transmission data, which is parallel data, is converted into serial data and transmitted to the frame synchronization unit 15. Also, it converts the received data, which is serial data from the frame synchronization unit 15, into parallel data and sends it out to the system bus.

On the other hand, the parity check unit 19 performs a parity check on the output using the output line address and parity. When there is a parity error (for example, when this output is not inverted by an odd number of bits), the occurrence of a failure is notified to the MPU 6 by an interrupt or the like.

[0007]

According to the above-mentioned prior art, the failure detection in the time slot control is performed by using the parity generated by the output from the line address register unit 10 (actually, the line address multiplexer unit 11). The parity check method is used to verify the validity of the output. According to this method, a failure due to a hardware failure in the line address register unit 10 and the line address multiplexer unit 11 can be detected. However, for example, a failure due to a hardware failure in the line address decoder unit 12 cannot be detected.

Therefore, when the line address decoder unit 12 is out of order, or when instructions from the MPU 6 and software are inappropriate, at the time of parity check,
I can't find any obstacles. As a result, control different from correct (predefined) time slot control is performed, and a failure is detected due to destruction of transmission / reception data. As described above, conventionally, detection of a failure is slow, which has been a hindrance to realizing a better nonstop system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time slot instruction check processing method capable of promptly checking a failure in time slot control that cannot be detected by the parity check method.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention, and a communication control processing unit (CCP) according to the present invention.
The main part of is shown. In this CCP, the line address register unit 10 holds a line address used by each time slot (or channel) when transmitting and receiving data.
The line address multiplexer 11 switches and outputs the output of the line address register 10 according to the number (time slot number) of the transmitted / received time slot. The output from the line address multiplexer 11 is decoded by the line address decoder 12, and one line address is selected.

The output of the line address decoder 12 is used for error checking (failure detection) in time slot control.
Is sent to the error check unit 14. In the error check unit 14, the time slot counter register unit 16 holds, for each line, the number of time slots that use the line. Time slot counter 17
Counts the number of time slots that use (used) each line in a predetermined period. The comparator section 18 compares the contents of the time slot counter register section 16 with the contents of the time slot counter section 17 at a predetermined timing.

[0012]

When transmitting / receiving data, the number of time slots is stored in the time slot counter register section 16 by the MPU 6 of the CCP (written and the line is activated). Prior to this, the line address is written into the line address register 10 by the MPU 6. The number of time slots represents the number of time slots that use the line for each line in a predetermined period of transmission and reception, for example, one frame, and is determined in advance. The line address represents a line address used by each time slot during a predetermined period of transmission and reception.

When a line is activated and transmission / reception is started, the time slot counter unit determines, for each line, how many times the line has been selected and output from the line address decoder unit 12 for each line during a predetermined period (how many times). Is used by the selected time slot. And
The comparator unit 18 performs the above-described comparison at a predetermined timing after a predetermined period. If the time slot control is normal, the result of the comparison should match. Thus, the comparator unit 18 determines that the time slot control is normal and abnormal, respectively, when both match and mismatch.

Therefore, for example, even when the line address decoder unit 12 fails or the time slot control (instruction) of the MPU 6 and software is improper, the failure can be promptly detected by the comparator unit 18.

[0015]

FIG. 2 is a block diagram of an embodiment. Computer 1 or C
The PU (central processing unit) is connected via a network 3 such as ISDN,
Sends and receives data to and from other computers and terminals. The computer 1 is connected to the network 3 via the CCP 2 according to the present invention. The CCP 2 performs a communication control process, for example, line status monitoring, error detection, and the like. The CCP 2 includes a line control unit 4 and a line corresponding unit 5.

FIG. 3 is a configuration diagram of the embodiment, showing the configuration of the CCP 2. The line control unit 4 includes an MPU (microprocessor unit) 6, a ROM (read only memory) 7,
M (read / write memory) 8 and an external interface unit 9. The line corresponding unit 5 includes a line address register unit (register unit) 10, a line address multiplexer unit (multiplexer unit) 11, a line address decoder unit (decoder unit) 12, a serial-parallel converter (converter) 13, and an error check unit. 14 and frame synchronization unit 1
Consists of five.

In the line control unit 4, the MPU 6
Along with the software (various programs) on the M7 and the RAM 8, various processes for communication control including time slot control are performed. The external interface unit 9 transmits and receives data to and from a host device, for example, the computer 1 shown in FIG. This transmission and reception is performed, for example, via a LAN (local area network).

In the line correspondence unit 5, the frame synchronization unit 1
5 performs data transmission / reception with the network 3 such as the ISDN shown in FIG. 2 while maintaining frame synchronization in a frame format (in the HDLC procedure). Also, the frame synchronization unit 15
Supplies a time slot number in a frame of a transmitted / received time slot to the multiplexer unit 11. Further, the frame synchronization unit 15 supplies a frame synchronization signal originally formed for frame synchronization to the error check unit 14 for time slot control (check). Therefore, the check of the time slot control is performed for each frame in units of one frame.

The register section 10 is composed of registers corresponding to each time slot of one frame. In each register, the line address used by each corresponding time slot is set and held by the MPU 6. Here, the parity of the line address is not set in the register section 10, as can be seen from the comparison with FIG. Therefore, the load on hardware and software for generating parity can be eliminated, and the size of the register unit 10 can be reduced.

The multiplexer unit 11 includes a register unit 1
From 0, each line address used in each time slot is input. The multiplexer unit 11 selects and outputs a line address used by the time slot of the number based on the supplied time slot number. That is,
The line address for the transmitted / received time slot is output.

The decoder section 12 decodes the output line address and selects one line of the address according to the decoded line address. This selection output is sent to the conversion unit 13 and the error check unit 14.

The conversion units 13 are provided for each of the lines. The conversion unit 13 corresponding to the selected line performs serial-parallel conversion of transmission / reception data. That is, the parallel data is converted into serial data for frame transmission and transmitted to the frame synchronization unit 15. Further, it converts the serial data received from the frame from the frame synchronizing unit 15 into parallel data and sends it out onto the system bus.

The error check section 14 is provided for each of the lines, and its detailed configuration is as shown in FIG. The error check unit 14 counts the number of time slots that actually use the corresponding line in one frame, and compares this with the number of time slots that should use the line (which can be obtained in advance). Perform an error check. As the timing signal, a frame synchronization signal is used.

The time slot counter register (TS)
In the register section 16, the number of times the line of the address is used by the time slot is written. This writing is performed for each line for each frame.

When receiving a certain frame synchronization signal, the time slot counter unit (TS counter unit) 17
The counting of the output of the decoder section 12 is started, and when the next frame synchronization signal is received, the counting of the frame is ended. This counting is performed so that “+1” is obtained when the corresponding line of the TS counter 17 is output from the decoder 12.

When receiving the "next frame synchronizing signal", the comparator section 18 takes in the contents of the TS register section 16 and the contents of the TS counter section 17 at this timing and compares them. If they match, the time slot control is determined to be normal, and no notification to the MPU 6 is made. On the other hand, if they do not match, it is determined that the time slot control is abnormal, and the MPU 6 is notified of this. This notification is based on, for example, an interrupt notification to the MPU 6. Therefore, the MPU 6 knows the time slot control abnormality at this time, and can perform a predetermined abnormality process.

[0027]

As described above, according to the present invention,
In the time slot instruction check processing for checking the validity of the time slot control, the failure detection in the time slot control is performed by comparing the number of time slots that actually use the line with the predetermined number of time slots that should use the line. As a result, even if the line address decoder unit is faulty or the software time slot control instruction is invalid, it is possible to promptly detect the fault caused by these and contribute to the realization of a better nonstop system. .

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a configuration diagram of an embodiment.

FIG. 4 is an explanatory view of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Computer 2 CCP 3 Network 4 Line control unit 5 Line correspondence unit 6 MPU 7 ROM 8 RAM 9 External interface unit 10 Line address register unit 11 Line address multiplexer unit 12 Line address decoder unit 13 Serial-parallel conversion unit 14 Error check unit 15 Frame synchronization section 16 Time slot counter register section 17 Time slot counter section 18 Comparator section 19 Parity check section

Claims (3)

(57) [Claims] 1. A line address register (10) for holding a line address used by each time slot, and a line address multiplexer for switching the output of the line address register (10) according to the number of the time slot being transmitted and received. (11) and a communication control processing device having a line address decoder (12) for decoding an output from the line address multiplexer (11), the number of time slots using each line being held for each line. Time slot counter register (16)
A time slot counter unit (17) for counting the number of time slots using each line for a predetermined period; and a time slot counter register unit (16) and a time slot counter unit (17) at a predetermined timing. And a comparator section (18) for comparing the contents of the above with the comparator section (18).
A time slot indication check processing method characterized in that when both match and mismatch, the time slot control is normal and abnormal, respectively. 2. A frame synchronizing unit (15) for transmitting and receiving data while maintaining frame synchronization in a frame format, wherein the frame synchronizing unit (15) includes the time slot counter unit (17) and a comparator unit (18). ) To supply a frame synchronization signal to the time slot counter unit (1).
7) performs the counting during a period from one frame synchronization signal to the next frame synchronization signal, and the comparator section (18) performs the comparison at the timing of the next frame synchronization signal. The time slot instruction check processing method according to claim 1. 3. The time slot instruction check processing method according to claim 2, wherein said frame synchronization section (15) supplies the time slot number to said line address multiplexer section (11).