JPH08272752A - Parallel processor - Google Patents

Abstract

PURPOSE: To prevent a packet fault from being propagated to a following packet by adding an end flag to a packet and detecting whether or not a received end flag matches with a correct value held on a reception side in advance. CONSTITUTION: When the end flag 292 transferred by a packet receiving buffer circuit is discrepant to the contents of an end flag register 230, the flag analyzing circuit 260 of a packet analyzing circuit 210 informs the fault analytic register 271 of a packet fault analyzing circuit 270 of the discrepancy by using an improper packet data length signal 263 showing the discrepancy, and the fault analytic register 271 sets an improper packet data length bit ON. And, an interrupt signal 805 is turned to be ON to inform a main storage control circuit 300 of the presence of the error in packet data length. Further, the improper packet data length signal 263 sets a reception stop state bit 237 ON and a packet reception control circuit stops receiving packets when a reception processing stop signal 238 is turned to be ON.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor in which a plurality of processor units transfer data via a network. In particular, the processor units are an instruction processing device, a main memory device, and a main memory device and a network. The present invention relates to a fault processing method for a parallel processor including a network adapter device that connects the two.

[0002]

2. Description of the Related Art Conventionally, as a network failure processing method in a parallel processor, an error correction code is added to a packet, which is a data transfer unit on the network, to detect that a bit error has occurred on the network. A method of improving the reliability of packet data in data transfer by performing error recovery as necessary is known. This is performed by adding an error correction code to a packet for transferring data (composed of a command field, a sequence field, a destination address field, a source address field, a data field, etc.). Also, using the destination address field and the source address field, if an inactive processor is routed to the destination, the processor node receiving the packet adds an error indicator to the packet,
It is sent back to the sending processor. Furthermore, if the processor detects that the packet is routed to the wrong processor from the error correction code, the error correction code corrects the error,
The packet is retransmitted via another route. Such a technique is described in JP-A-4-139566.

As another conventional technique, there is known a system in which a system down does not occur when a part of links (channels) in a network fails. this is,
As shown in FIG. 9, in a parallel computer having a 4 × 4 two-dimensional torus type network configuration, as indicated by the broken line in FIG. 9, when the link in the third column fails, four processors (C13 , C23, C33, C43) are set in the through state in the X direction to generate a network having a 4 × 3 two-dimensional torus structure and prevent failures in the entire network. Such a technique is described in JP-A-4-287265.

[0004]

In the technique of interprocessor communication of the parallel computer, when a certain packet is lost in the network in the transfer of a packet or a data length failure occurs, the following process is performed. Therefore, there is a possibility that the data of the packet to be received by the user may be mistaken for the lost data portion of the certain packet, and as a result, the certain packet and the subsequent packet may be received with an incorrect configuration. It was In addition, even if a packet is lost, there is a problem that a subsequent packet is erroneously received.

In a conventional parallel processor in which a node is composed of a processor and a main memory, and a plurality of these nodes are connected by a network, a failure occurs in the main memory during data transfer and the data should be transferred. Access to data in main memory may not be possible. In this case, the transmission side processor cannot complete the transmission process of the data transfer, and the reception processor cannot complete the reception process, and the network route between the corresponding processors remains occupied as the route for the data transfer. It becomes a blocked state. As a result, all packet transfers using this network route are blocked, which may lead to failure of the entire network.

It is an object of the present invention to detect packet data length corruption and loss of packet data in a packet, and to prevent the failure of the packet from propagating to subsequent packet failures. Is to provide packet communication.

Another object of the present invention is to obstruct the packet communication between processors in a parallel processor by eliminating the influence of the main memory failure of the processor of a certain node on the packet communication between the processors, thereby becoming an obstacle to the entire network. It is to provide packet communication between processors that can avoid the above.

[0008]

To achieve the above object, in a parallel processor composed of a plurality of processors and a network capable of transferring packets between the arbitrary processors, the transmitting side processor At the start of transfer, a start code indicating that the packet transfer is started is transferred to the network prior to the packet, and an end code indicating completion of the packet transfer is transferred when the transfer of the packet is completed. , If the start code and end code that the receiving processor holds in advance do not match the received start code and end code,
A judging means for judging that the packet is abnormally received is provided.

In the parallel processor, the judging means regards the received data located after a predetermined data amount from the received start code, which is determined by using the data length in the packet, as the end flag. To have.

Further, in the parallel processor, each of the processors is composed of a network adapter device and an instruction processing device, and the network adapter device is capable of receiving a packet transferred from the network and the network. If the network adapter device has a reception stop state in which a packet transferred from is not received, and the network adapter device has the determination means and is in the receivable state and the determination means determines abnormal reception, the command processing device is Generate an interrupt,
When the reception is stopped, the network adapter device receives the data corresponding to the start flag from the network when the reception processing is enabled from the reception stopped condition by the instruction from the instruction processing device, and compares with the start code. If the start code does not match, the reception process is not restarted. If the start code matches, the reception process is restarted, and a packet resynchronization means is provided.

Next, in a parallel processor composed of a plurality of processors and a network capable of transferring packets between the arbitrary processors, the transmitting side processor starts the packet transfer at the start of packet transfer. Has a means for transferring a start code indicating to the network prior to the packet, and the receiving processor starts the received code when the start code held in advance matches the code received from the network. And a means for always receiving the data from the network following the received code as a code preceding a new packet.

Next, it is composed of a plurality of processors and a network capable of transferring data between any of the processors, and each processor includes an instruction processing device, a main memory device, and the main memory device. And a network adapter device that connects the network, the processor on the transmission side transfers the data to be transferred on the network between the main memory and the network adapter device while When the data transmission between the main memory and the network adapter device becomes impossible during the operation of the transmission device, the network adapter device is configured to transmit the data to the network. Generates, sends, and sends arbitrary data until the data length of the To have a means to end the process.

Next, in the parallel processor,
The arbitrary data is means for generating data indicating an error, and the processor on the transmission side transfers a start code indicating start of the packet transfer to the network prior to the packet at the start of packet transfer, And having means for transferring an end code indicating completion of the packet transfer when the transfer of the packet is completed,
When the start code and end code held in advance by the receiving processor match the received start code and end code, and the data of the received packet indicates an error, the instruction processing device of the receiving processor This is accomplished by having a means of interrupting

[0014]

According to the above means, when transmitting a packet to the network, the transmitting processor transmits a fixed code (hereinafter referred to as a start flag) before transmitting the packet body.
Is sent to the network, and when the packet transfer is completed, a certain code (hereinafter referred to as an end flag) is sent to the network. When the reception processor receives the data corresponding to the start flag, it decodes it, and if it matches the start flag, it starts the reception process as the start of a new packet, and if it does not match, it does nothing. And
When the reception of the packet is completed, the data corresponding to the end flag is continuously received, and when the data is decoded and coincides with the end flag, the packet is normally received and the reception process is ended. If the end flags do not match, it indicates that the packet data length is incorrect or the packet data has been lost. Therefore, this mismatch allows detection of an error on the network. As a result, the receiving side processor can generate an interrupt to the instruction processing device, and the receiving side can process the reception abnormality by the instruction processing device.

When data cannot be read due to a failure of the main memory on the transmission side, the processor on the transmission side automatically generates and transmits dummy data with a parity error corresponding to the data length, and finally ends. Send the flag.
Therefore, the transmission side can complete the transmission process.
Further, the receiving side can receive the packet having the uniform data length, so that the receiving process can be completed. As a result, the communication path between the transmission side and the reception side is opened, and it is possible to prevent the system from going down due to the blockage of the network path between the corresponding processors. The receiving side can discard the data because it is a parity error. On the other hand, if data cannot be written due to a failure in the main memory on the receiving side,
Although the transfer from the network adapter device to the main storage device is stopped, the network adapter device continues the receiving process until the end flag is received, so that the receiving process can be completed. As a result, the communication path between the transmission side and the reception side is opened, and it is possible to prevent the system from going down due to the blockage of the network path between the corresponding processors.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of a parallel processor to which the present invention is applied. Each processor PU is a network NW
Are connected to each other, and communication between the processor PUs at arbitrary positions is possible (in FIG. 1, the processor PUs are connected to each other).
From processor PU-0 to processor PU-n,
(N + 1) units are shown). Each processor PU includes an instruction processing device IP, a main memory processing device MS (the main memory itself is also included in the main memory processing device), an input / output processing device IOP,
It is composed of a network adapter device ADP that sends and receives packets to and from the network NW. The instruction processing device IP and the main memory processing device MS are connected to the processor bus P.
The main storage device MS, the input / output processing device IOP, and the network adapter device ADP are connected by BUS,
It is connected by the system bus SBUS.

FIG. 2 shows the detailed structure of the network adapter ADP for transmitting and receiving packets to and from the network NW. The network adapter ADP is composed of a transmission circuit 100 that transmits a packet to the network, a reception circuit 200 that receives a packet from the network, and a main memory control circuit 300 that controls access to the main memory processing device. The transmission circuit 100 includes a packet configuration circuit 110 that assembles packets and a DMA circuit 120. The receiving circuit 200 is composed of a packet receiving circuit 803 for receiving a packet and a packet analyzing circuit 210 for analyzing the receiving state of the packet. Further, the main memory control circuit 300 includes a bus control circuit 310 that controls the system bus SBUS and a failure analysis circuit 320 that performs failure analysis.

FIG. 3 shows the structure of a packet 400 which is a transfer unit. A packet is composed of a packet header and packet data. The packet header is a destination processor address, an extension field length indicating the length of the extension field, a packet data length indicating the length of packet data, a transmission control information field for controlling transmission,
It is composed of a write address offset and an extension field used for OS debugging. Here, 3 of processor address, extended field length, and packet data length
One element is duplicated, and the final bit of each element is a parity error check bit.
When a parity error occurs, the processor address, extended field length, and packet data length that did not cause an error are used. In the present invention, when the above packet is transferred on the network NW, prior to the packet transfer,
In the system, a predetermined constant code, that is, a start flag is transmitted. This start flag is
Next, it indicates that the beginning of the packet comes. As the value of this code, any code can be used as long as it is uniquely determined in advance in the system to which the present invention is applied. Further, following the completion of packet transfer, a predetermined constant code, that is, an end flag, is transmitted in the system. This end flag indicates that the data before the flag is the end of the packet. As the code of this end flag, any code can be used as long as it is uniquely determined in advance in the system to which the present invention is applied.

Although the transfer data width is shown as 2 bytes in FIG. 3, this data width can be determined according to the data width of the network of parallel computers (thus, the packet data width is shown in FIG. 3). Not limited to 2 bytes). For example, the network NW in FIG.
Since the packet width of FIG. 3 is 16 bits, it is a network capable of simultaneously transferring 16 bits.

(1) First, the transmission processing operation will be described with reference to FIG.
This will be described with reference to FIGS. 4 and 5. The instruction processing device IP generates the transmission control word 10 on the main memory processing device, and the processor bus PBUS, the main memory device MS, and the system bus SB.
A transmission instruction is issued to the network adapter device ADP via the US. Further, the instruction processing device IP includes a processor bus PBUS, a main memory device MS, a system bus SBUS.
The start address of the transmission control word is transferred to and written in the transmission control word address start register 330 in the network adapter ADP via.

In the main memory control circuit 300 of FIG. 2, a transfer instruction signal 301 for instructing data transfer is sent to the transmission circuit 100 based on the start address of the transmission control word written in the transmission control word address start register 330. Instruct to start transmission. In addition, the main memory control circuit 300
Reads the transmission control word 10 from the main memory device MS by the bus control circuit 310, and transmits the transmission control word transfer signal 3
Along with 02, the transmission control word 10 read from the main memory processing device is transferred to the transmission circuit 100. Further, the main memory control circuit 300 extracts the address of the main memory in which the data to be transmitted is stored from the transmission control word 10 and sets it in the transmission data address register 340. Further, the main memory control circuit 300 outputs a transfer instruction signal 301 to the DMA circuit 120.

The packet configuration circuit 110 (FIG. 4) stores a start flag indicating the start of the packet to be transferred when the transfer instruction signal 301 transferred from the main memory control circuit 300 turns on indicating the transmission start instruction. The packet selection circuit 180 selects the content of the start flag register 120 (that is, the start flag) and transfers it from the network interface 500 to the network. The packet configuration circuit 110 also writes the transmission control word 10 transferred from the main memory control circuit 300 into the transmission control word register 140. In addition, the packet construction circuit 110 sends the transmission control word 10 to the packet header construction circuit 150 which assembles the packet header, and also sends the packet length field 141 to the DMA circuit 12.
0 (FIG. 5) to the DMA control circuit 800. Packet header configuration circuit 150 in packet configuration circuit 110
Constitutes a packet header, and the packet selection circuit 180
Transferred to. When receiving the packet header, the packet selection circuit 180 transfers the packet header to the network NW continuously after transferring the start flag transmitted earlier.

In the DMA circuit 120 shown in FIG. 5, when the data transmission instruction signal 301 is turned on, the DMA control circuit 800 turns on the packet data access request signal 371, and the bus control circuit 31 of the main memory control circuit 300 is turned on.
A packet data access request is issued to 0. When the packet data access request signal 371 is turned on, the bus control circuit 310 of the main memory control circuit 300 starts the operation of reading the data of the main memory processing device from the address indicated by the transmission data address register 340 and transferring it to the DMA circuit 120. To do. The DMA circuit 120 temporarily sets the read data in the transmission data buffer control circuit 801 in the DMA circuit 120. Then, when the data of the packet data length is read, the packet data access request signal 371 is turned off. On the other hand, the DMA circuit 120
Is the buffer control circuit 8 using the read data line 351.
The data set to 01 is transferred to the packet selection circuit 180. At this time, the packet data transmission request signal 381 for requesting the packet selection circuit 180 to transfer the packet data to the network is turned on. When there is no more data to transfer, the DMA control circuit turns off the packet data transmission request signal 381.

When the packet data transmission request signal 381 is ON, the packet selection circuit 180 of the packet configuration circuit 110 shown in FIG.
When the transfer data transferred from the MA circuit 120 is transferred to the network and the packet data transmission request signal 381 from the DMA circuit 120 is turned off, the end flag register 120 that stores the end flag indicating the end of the packet to be transferred. Content (ie end flag)
Is read from the end flag register 120 and transferred to the network.

In this way, when transmitting a data packet to the destination processor via the network, the transmitting side processor adds a start flag before the packet and adds an end flag after the packet. be able to. The transmission processing operation has been described above with reference to FIGS. 2, 4, and 5.

(2) Next, the receiving process will be described with reference to FIGS. 2, 6 and 7. First, a normal reception process when there is no abnormality in the network will be described.

The receiving circuit 200 of FIG.
When a packet reception instruction is received from W through the network interface 600, the packet analysis circuit 210 extracts the data corresponding to the start flag from the received data.
It is taken into the flag analysis circuit 260 in (FIG. 6). The flag analysis circuit 260 compares the contents of the start flag register 220 (that is, the start flag), which stores the value of the start flag in advance, with the data corresponding to the fetched start flag. The next data to be received is the exact beginning of the packet, and therefore, the packet reception circuit 803 (FIG. 7) is sent with the reception start instruction signal 261 (signal 261).
Turn on). If the comparison result does not match, the flag analysis circuit 260 does nothing because the data to be received next is not the head of the packet. The receiving circuit 200 is
Further, the data following the start flag (the header portion of the received packet) is received, and the received data is set in the packet header register 240 in the packet analysis circuit 210. Then, the processor address in the packet header, which is the destination of the packet, is transferred to the processor number comparison circuit 250 (here, the received processor address is the same as the received processor address because of normal reception). Explained as).

The packet analysis circuit 210 transfers the packet length 243 from the header register 240 recording the packet header to the packet reception circuit 803, and also transfers the write address offset 242 to the adder 236. The transferred write address offset is added to the content of the write address register 235 and transferred to the main memory control circuit 300 by the packet analysis circuit 210 through the reception destination address line 804. As a result, the main memory processing device can determine the data storage location when receiving data.

The packet reception control circuit 280 in the packet reception circuit 803 receives the packet reception instruction signal 261 from the flag analysis circuit 260 of the packet analysis circuit 210, and instructs the packet reception buffer 290 to receive the packet. The instruction signal 283 is turned on.

The packet reception control circuit 280 uses the packet length 243 sent from the packet analysis circuit 210 to take in packet data equal to the packet length from the network to the reception buffer 290, and turns off the packet reception instruction signal 283. To do. Further, the packet reception control circuit 280 is in parallel with the above operation, and in response to the reception start instruction signal 261 from the packet analysis circuit, the main memory control circuit 30.
For 0, the packet data write instruction signal 282 is turned on, the packet data is taken out from the packet reception buffer 290, and the write data is transferred to the main memory control circuit 300 through the write data signal line 291.

When the packet data write instruction signal 282 is turned on, the main memory control circuit 300 issues a write request to the main memory device MS for a continuous area starting from the reception address transferred from the reception destination address line 804, The write data transferred through the write data signal line 291 is transferred through the system bus SBUS.

The packet reception buffer 290 of the packet reception circuit 803 receives data equal to the packet length,
Further, the data corresponding to the position of the end flag of the received packet is fetched from the network. Then, the received data corresponding to the position of the end flag is passed through the data line 292 to the flag analysis circuit 26 in the packet analysis circuit 210.
Transfer to 0. Further, the packet reception control circuit 280 of the packet reception circuit 803 receives an end flag transfer instruction indicating that the packet reception buffer 290 has taken in the packet data having the same packet length from the network and sent the data corresponding to the position of the end flag to the packet analysis circuit 210. The signal 281 is transferred to the packet analysis circuit 210.

When the flag analysis circuit 260 of the packet analysis circuit 210 receives the end flag transfer instruction signal 281 and the data 292 corresponding to the position of the end flag of the packet from the packet reception circuit 803, the end flag value stored in advance is stored. The contents of the flag register 230 (that is, the end flag) is compared with the data corresponding to the position of the fetched end flag. If the comparison results match, the received end flag is judged to be correct, and the received packet is judged to have been received correctly without the packet length data being lost in the network, Reception completion signal 26 indicating completion of packet reception
2 is sent to the packet reception control circuit 280.

The packet reception control circuit 280 completes the reception process when it receives the reception completion signal 262 from the flag analysis circuit 260 of the packet analysis circuit 210.

As described above, according to the above-described embodiment, the start side and the end of the packet are added with the start flag and the end flag predetermined by the system at the transmitting side and transmitted, and the receiving side starts. By checking the values of flags and end flags, and by checking the number of received data from the start flag to the end flag, it is checked whether or not packet data could be transferred without being lost in the network. can do. The values of the start flag register 220, the end flag register, the write address register, etc. are assumed to be set in advance using the signal line 372.

(3) Next, the reception process when a network failure occurs will be described with reference to FIGS. 2, 6 and 7.

In the processor number comparison circuit 250 of the packet analysis circuit 210, the processor address in the packet header indicating the destination of the packet is compared with the processor address of the processor that has received the packet. The processor number mismatch signal 272 indicating that the packet having the destination address is received is turned on, and the packet reception control circuit 280 and the packet failure analysis circuit 270 in the packet reception circuit 803 are turned on.
Transfer to. The packet failure analysis circuit 270 turns on the processor number mismatch bit in the failure analysis register 271 indicating a failure when the processor number mismatch signal 272 is turned on, and further turns on the interrupt signal 805.
The main memory control circuit 300 is notified of the failure occurrence. On the other hand, when the packet reception control circuit 280 receives the processor number mismatch signal 272, the packet reception control circuit 280 discards the currently receiving packet.

When the packet reception buffer 290 of the packet reception circuit 803 detects a parity error in the received data, it turns on the parity error signal 293 indicating the parity error and notifies the packet failure analysis circuit 270 of the packet occurrence. The packet failure analysis circuit 270
When the parity error signal 293 is turned on, it is determined that a parity error has occurred, and the parity error bit of the failure analysis register 271 is set. After that, interrupt signal 8
05 is turned on to notify the main memory control circuit 300 of the failure occurrence.

The flag analysis circuit 260 of the packet analysis circuit 210 has an end flag 292 and an end flag register 230 transferred from the packet reception buffer circuit 290.
If the contents of the packet do not match, the packet failure analysis circuit 270 using the packet data length invalid signal 263 indicating the mismatch.
The failure analysis register 271 is notified of the inconsistency, and the failure analysis register 271 sets the packet data length incorrect bit indicating that the packet data length is incorrect to ON.
Then, the interrupt signal 805 is turned on to notify the main memory control circuit 300 that the packet data length has an error. Further, the packet data length invalid signal 263 indicating that the end flag 292 and the end flag register 230 do not match is indicated in the reception stop state bit 237 indicating whether the reception is possible or not. Set on. Then, the reception stop status bit 23
The reception stop signal 238 which is the output of No. 7 is transferred to the packet reception control circuit 280. Packet reception control circuit 280
Stops the packet receiving process when the receiving process stop signal 238 is turned on. Even if the reception instruction is transferred from the network, the reception process is not performed.

The main memory control circuit 300 uses the interrupt signal 80
When receiving 5, the system bus SBUS, the main memory M
Instruction processor IP via S and processor bus PBUS
Send an interrupt signal to. The instruction processing device IP executes the process for the interrupt, and receives the reception stop state bit reset signal 311 from the reception stop state bit 237 in the network adapter device ADP via the processor bus PBUS, the main storage device MS, and the system bus SBUS. When turned off, the reception stop signal 238 is also turned off, and the network adapter device ADP restarts the reception process.

As described above, when the above-mentioned error occurs in the packet on the network, the network adapter device suspends the receiving process and enters the receiving process stop state. Therefore, even if data loss occurs in the data packet, the network adapter device does not mistake the data of the following packet for the lost data. Also, since the data adapter device notifies the instruction processing device of the error occurrence as an interrupt,
The instruction processor can refer to the reception stop status bit and take appropriate error countermeasures. After that, the instruction processing device restarts the network adapter and controls the state of the network adapter device from the reception stopped state to the receivable state, so that the network adapter device resumes normal reception processing assuming that the error has been recovered. You can

(4) Next, the transmission and reception processing in the case where the main memory access becomes impossible due to a failure in the main memory processing device MS will be described with reference to FIGS. 2, 5 and 8.

First, a case will be described in which access to the main storage processing device becomes impossible due to a failure in the main storage device MS during the transmission process. The main memory control circuit 300 is a DMA
Packet data access request signal 371 from circuit 120
When the access request to the main memory processing device MS is received by the bus control circuit 310, the access request is sent to the main memory processing device MS by turning on the request request signal 830 which is a data request to the main memory. Then, when the response signal 302 which is a response to the access request from the main memory processing device MS is turned on, the quest request signal 830 is turned off. In addition, this quest request signal 8
30 and the response signal 302 are simultaneously transferred to the bus failure analysis circuit 320 (FIG. 8).

The bus failure analysis circuit 320 of FIG. 8 has a timer circuit 340 having a timer therein. When the request request signal 830 is turned on, the timer value is reset and then the timer is activated to measure the time. To start.
Further, when the response signal 302 to the request request from the main memory processing device MS is turned on, the time measurement is stopped.
The measured timer value is transferred to the comparator 360, and the content of the request response time register 820 holding the predetermined request response time to the main memory processing device MS (that is, the request response time). ) Is compared by the comparator 360. An upper limit value of the request response time is set in the request response time register 820, and if the timer value is larger than this upper limit value,
The bus fault signal 361 is turned on because the bus fault has occurred. The contents of the request response time register 820 are stored in advance in the system bus SBU from the input / output device IOP or the like.
It is set via S. The bus failure analysis circuit 320
The system bus SBUS failure signal 361 is sent to the DMA circuit 1
Data selection circuit 350 and DMA control circuit 8 in 20
00 and the packet reception control circuit 280 of the packet reception circuit 803.

The data selection circuit 35 in the DMA circuit 120
0 selects dummy data generated by the dummy data generation circuit 810 when the bus fault signal 361 is turned on and transferred through the data line 811, and the dummy data is transferred to the packet configuration circuit 110 via the read data line 351 to be dummy. Transfer data. The dummy data generation circuit 810
May be operated when the bus fault signal 361 is turned on, or may be always operated. here,
The dummy data generated by the dummy data generation circuit 810 has a parity error, and the processor that receives the packet including this dummy data discards this data. On the other hand, the DMA control circuit 800 in the DMA circuit 120 turns off the packet data access request signal 371 when the bus fault signal 361 turns on. As a result, the main memory control circuit 300 suspends the data transfer from the main memory MS in which the access error has occurred.

The packet configuration circuit 110 transfers the data corresponding to the packet length field of the packet header to the network NW, and finally transfers the end flag, as in the normal transfer. The processor on the receiving side performs the above-mentioned error processing because the received data is a parity error.

As a result, even if an abnormality occurs in the access to the main memory device MS in the sending processor, the network adapter device of the sending processor sends the packet being sent without interruption, thus completing the sending process. Therefore, it is possible to open the communication link that has been established on the network with the receiving side, and the access failure to the storage device in the transmitting processor does not have a great influence on the communication path of the entire network. .

Next, a case will be described in which main memory access becomes impossible due to a failure in the main memory processing device MS during the reception processing. The process up to the generation of the bus fault signal 361 is the same as the case of the transmission process, and a description will be given from the time when the bus fault signal 361 is turned on. The bus fault signal 361 is transferred to the packet reception control circuit 280 of the packet reception circuit 803.

The packet reception control circuit 280 of the packet reception circuit 803, when the bus fault signal 361 is turned on,
Turn off the packet data write instruction signal 282,
As a result, the writing of the packet data to the main memory processing device MS is stopped. However, the packet receiving circuit 803
Overwrites the received packet data in the packet reception buffer 290 until it detects the reception end flag indicating the end of the packet. As a result, even if the receiving processor has an abnormal access to the main storage device MS, the network adapter device of the receiving processor receives the packet being received without interruption,
The reception process can be completed, and therefore the communication link established on the network with the transmission side can be released, and the access failure to the storage device in the reception processor has a great impact on the communication path of the entire network. Never give.

[0050]

According to the above invention, a circuit for adding an end flag to a packet and detecting whether or not the received end flag matches the correct end flag value previously held on the receiving side is provided. Therefore, it becomes possible to detect the illegal reception of the packet data length, and if there is an error in the data length field of the packet header or the packet data is lost on the network, the specified number of packet data will be normal. Immediately and accurately can detect that it was not able to receive. As a result, the data of the subsequent packet will not be mistaken for the data of the preceding packet.

Further, the transmitting side always adds a start flag to a new packet for transmission, and when the receiving side receives the start flag, it discards the packet data being received which has not been received until now, Since the packet is interpreted as a new packet and reception is started, even if the data loss of a certain packet occurs on the network, the receiving side normally receives from the beginning of the subsequent packets after the packet with the data loss. it can.

Further, when data cannot be read due to a failure of the main memory on the transmission side, the processor on the transmission side transmits dummy data with a parity error corresponding to the data length, and finally transmits an end flag. . Therefore, the transmission side can complete the transmission process. Further, the receiving side can receive the packet having the uniform data length, so that the receiving process can be completed. As a result, the communication path between the transmission side and the reception side is opened, and it is possible to prevent the system from going down due to the blockage of the network path between the corresponding processors. The receiving side can discard the data because it is a parity error.

On the other hand, when data cannot be written due to a failure of the main memory on the receiving side, the processor on the receiving side stops the transfer from the network adapter device to the main memory device, but the network adapter device Since the reception process of packet reception is continued until the end flag is received, the reception process can be completed. As a result,
The communication path between the transmission side and the reception side is opened, and it is possible to prevent the system from going down due to the blockage of the network path between the corresponding processors.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 shows a configuration of a network adapter device ADP.

FIG. 3 shows a structure of a packet which is a transfer unit.

FIG. 4 shows a configuration of a packet configuration circuit in a transmission circuit in the network adapter device ADP.

FIG. 5 shows a configuration of a DMA circuit in a transmission circuit in the network adapter device ADP.

FIG. 6 shows a configuration of a packet analysis circuit in a reception circuit in the network adapter device ADP.

FIG. 7 shows a configuration of a packet receiving circuit in a receiving circuit in the network adapter device ADP.

FIG. 8 shows a configuration of a failure analysis circuit in a main memory control circuit in the network adapter device ADP.

FIG. 9 shows a conventional technique.

[Explanation of symbols]

 IP command processor MS main memory processor IOP input / output processor ADP network adapter device NW network 100 transmitter circuit 200 receiver circuit 300 main memory controller 110 packet configuration circuit 120 DMA circuit 210 packet analysis circuit 803 packet receiver circuit 310 bus control circuit 320 bus failure analysis circuit 120 start flag register in transmission circuit 130 end flag register 810 in transmission circuit dummy data generation circuit 220 start flag register in reception circuit 230 end flag register 260 in reception circuit 260 flag analysis circuit

Claims (6)

[Claims] 1. A parallel processor comprising a plurality of processors and a network capable of transferring packets between any of the processors, wherein a transmitting side processor starts the packet transfer at the start of packet transfer. Forwards the indicated start code to the network prior to the packet, and
When the transfer of the packet is completed, it has means for transferring an end code indicating completion of the transfer of the packet, and the start code and end code held in advance by the receiving processor match the received start code and end code. If not, a parallel processor having a judging means for judging that the packet is abnormally received. 2. The determining means considers received data, which is determined by using the data length in the packet and is located after a predetermined amount of data from the received start code, as the end code. A parallel processor according to item 1. 3. A parallel processor comprising a plurality of processors and a network capable of transferring packets between the arbitrary processors, wherein a transmitting side processor starts the packet transfer at the start of packet transfer. The receiving side processor has means for transferring the indicated start code to the network prior to the packet, and the reception side processor starts the received code when the start code held in advance matches the code received from the network. A parallel processor, characterized in that it has means for always receiving the data from the network following the received code as a code preceding a new packet. 4. Each of the processors comprises a network adapter device and an instruction processing device, and the network adapter device is in a reception processable state capable of receiving a packet transferred from the network and a packet transferred from the network. The network adapter device has the determination means, and when the determination means determines that the reception is abnormal, the network adapter device has an interrupt to the instruction processing device. In the reception stop state, the network adapter device receives the data corresponding to the start flag from the network when the reception processing state is changed from the reception stop state according to the instruction from the instruction processing device, and compares the start flag with the start code. , If the start code does not match, the receiving process Does not start in the case of matching the start code is to resume the reception processing, the parallel processor of claim 1, wherein the resynchronize packet. 5. A plurality of processors and a network capable of transferring data between any of the processors, wherein each processor comprises an instruction processing device,
In a parallel processor including a main storage device and a network adapter device that connects the main storage device and the network, the processor on the transmission side transfers data on the network between the main storage device and the network adapter device. When the data transfer between the main memory and the network adapter device becomes impossible during the operation of the transmission unit, the transmission unit transmits the data to the network while transferring the data. The parallel processor, wherein the network adapter device has means for generating and transmitting arbitrary data until the data length to be transferred by the transmission side processor, transmitting the arbitrary data, and ending the transmission process. 6. The parallel processor according to claim 5, wherein the arbitrary data is means for generating data indicating an error, and the processor on the transmission side starts the packet transfer at the start of packet transfer. A start code stored in the receiving processor in advance, which has means for transferring a start code indicating the packet to the network prior to the packet, and transmitting an end code indicating the completion of the packet transfer when the packet transfer is completed. When the code and end code match the received start code and end code, and the data of the received packet indicates an error, the instruction processor of the receiving processor is interrupted. Parallel processors to do.