JPS59200365A - Transfer system of control information - Google Patents
Transfer system of control informationInfo
- Publication number
- JPS59200365A JPS59200365A JP58074834A JP7483483A JPS59200365A JP S59200365 A JPS59200365 A JP S59200365A JP 58074834 A JP58074834 A JP 58074834A JP 7483483 A JP7483483 A JP 7483483A JP S59200365 A JPS59200365 A JP S59200365A
- Authority
- JP
- Japan
- Prior art keywords
- information
- processing system
- information processing
- output
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1497—Details of time redundant execution on a single processing unit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Retry When Errors Occur (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、互に情報通信をおこなう二つの情報処理シス
テムにおいて、情報を送出する側の情報処理システムが
故障した場合でも、誤った情報が受信側の情報処理シス
テムへ転送されることを防止する制御情報転送方式に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention is directed to two information processing systems that communicate with each other, and even if the information processing system on the sending side fails, erroneous information can be transmitted to the receiving side. This invention relates to a control information transfer method that prevents information from being transferred to an information processing system.
技術の背景
従来、プロセッサの故障を検出する手法としては、ソフ
トウェアによシ一定時間内にリセットするタイマを設け
て金物の正常性およびソフトウェアの正常性をチェック
する手法が用いられている。BACKGROUND OF THE INVENTION Conventionally, as a method for detecting a failure in a processor, a method has been used in which a timer is provided in software to be reset within a certain period of time and the normality of hardware and software is checked.
また電子交換機においては、一定時間ごとに擬似的に呼
を発生させ、所要の呼接続処理がおこなわれるかどうか
をチェックする外部監視回路を設ける手法も用いられて
いる。ソフトウェアによるプロセッサの故障検出は、プ
ロセッサが故障すれば、リセットされるべきタイマがリ
セットされずオーバフローする。また電子交換機におけ
る外部監視回路では接続動作が完了されないことを容易
に検出できる。Furthermore, in electronic exchanges, a method is used in which an external monitoring circuit is provided which generates a pseudo call at regular intervals and checks whether or not the required call connection processing is performed. In software-based processor failure detection, if a processor fails, a timer that should be reset is not reset and overflows. Furthermore, an external monitoring circuit in the electronic exchange can easily detect that the connection operation is not completed.
従来技術と問題点
従来の故障検出手法のみを用いても故障の発見、は可能
であるが、故障発見に至るまでに時間を要し、そ−の間
（送出された異常な情報が受信側の情報処理システムへ
転送され、受信側の情報処理システムをじよう乱させて
しまうという欠点を有していた。Conventional technology and problems Although it is possible to discover failures using only conventional failure detection methods, it takes time to discover the failure, and during that time (the abnormal information sent is This has the disadvantage that the information is transferred to the information processing system on the receiving side, causing a considerable disturbance to the information processing system on the receiving side.
発明の目的
本発明の目的は、従来の欠点を除去するために、送信側
情報処理システムが故障しても、異常な情報を受信側の
情報処理システムへ送出しない手段を備えた制御情報転
送方式を提供するもので、以下図面について詳細に説明
する。OBJECTS OF THE INVENTION An object of the present invention is to provide a control information transfer system having a means for not sending abnormal information to a receiving information processing system even if the transmitting information processing system fails, in order to eliminate the drawbacks of the conventional art. The drawings will be described in detail below.
発明の実施例
図は本発明の実施例であって、太線は情報線を示し、細
線は制御線を示す。１は送信側情報処理、 システム、
２は送信側情報処理システム１のアドレスバス、３は送
信側情報処理システム１のデータバス、４および５はそ
れぞれアドレスノ（ス２およびデータバス３のバス情報
の受信回路、６はアドレスバス２の情報を一時蓄積する
レジスタ、７はアドレスバス２の内容が自装置の番号と
一致しているかどうかをチェックする装置番号照合回路
、８は装置番号照合回路７における照合の結果、自装置
あてであることが判った場合に駆動されるタイミング制
御回路、９はデータバス３の情報を一時蓄積するレジス
タ、１０〜１４は論理積回路、１５は論理積回路ｌＯの
出力情報を一時蓄積するレジスタ、１６はレジスタ９お
よび１５の出力情報を比較して一致しているかどうかを
判定する比較器、１７は受信側情報処理システムである
。また、７０は装置番号照合回路７の出力、８０〜８５
はタイミング制御回路８の出力、匍はレジスタ９の出力
、１３０は論理積回路１３の出力、１４０は論理積回路
１４の出力、１５０はレジスタ１５の出力、１６０は比
較器１６での比較の結果、一致した場合に出力される一
致出力、１６１は比較器１６での比較の結果、不一致の
場合に出力される不一致出力である。Embodiments of the Invention The figures show embodiments of the invention, in which thick lines indicate information lines and thin lines indicate control lines. 1 is the sending side information processing, system,
2 is an address bus of the transmitting side information processing system 1, 3 is a data bus of the transmitting side information processing system 1, 4 and 5 are bus information receiving circuits for address bus 2 and data bus 3, respectively, and 6 is an address bus 2. 7 is a device number verification circuit that checks whether the contents of the address bus 2 match the number of the own device. 8 is a register that, as a result of the verification in the device number verification circuit 7, indicates that the address is addressed to the own device. 9 is a register that temporarily stores information on the data bus 3; 10 to 14 are AND circuits; 15 is a register that temporarily stores output information of AND circuit IO; 16 is a comparator that compares the output information of registers 9 and 15 to determine whether they match; 17 is a receiving side information processing system; 70 is the output of the device number matching circuit 7; 80 to 85;
is the output of the timing control circuit 8, 匍 is the output of the register 9, 130 is the output of the AND circuit 13, 140 is the output of the AND circuit 14, 150 is the output of the register 15, and 160 is the result of comparison in the comparator 16. , a coincidence output that is output when they match, and 161 a mismatch output that is output when there is a mismatch as a result of the comparison in the comparator 16.
本回路は、送信側情報処理システム１がアドレスバスお
よびデータバス２．３に情報を出力することで動作を開
始する。受信回路４．５によシ受信した第１回目の情報
はレジスタ６．９にそれぞれ一時蓄積される。装置番号
照合回路７はレジスタ６の情報を用いて自装置あてであ
ること全判定するとタイミング制御回路８を起動する。This circuit starts operating when the transmitting side information processing system 1 outputs information to the address bus and data bus 2.3. The first information received by the receiving circuit 4.5 is temporarily stored in the register 6.9. The device number verification circuit 7 uses the information in the register 6 to activate the timing control circuit 8 when it completely determines that the message is addressed to its own device.
タイミング制御回路８は、第１回目の情報ということで
出力８２ヲ活性化させ、論理積回路１０ｔ−動作させて
レジスタ９に蓄積されている情報をレジスタ１５にも入
力させる。The timing control circuit 8 activates the output 82 because it is the first information, operates the AND circuit 10t, and inputs the information stored in the register 9 to the register 15 as well.
送信側情報処理システム１は、引き続き同一情報の第２
回目の送出をおこなう。この場合、タイミング制御回路
８は第２回目であることからあらかじめ出力８１を活性
化させてレジスタ９ｔ−クリアしておく。レジスタ９に
第２回目の情報が格納されるとタイミング制御回路８は
出力門を活性化させ、比較器１６ヲ動作させる。両者の
情報が同一であれば、比較器１６は一致出力１６０ヲ活
性化させタイミング制御回路８に動作の継続を指示する
。第３回目以降の情報受信の際も同様な動作となる。The sending side information processing system 1 continues to transmit the same information to the second
Perform the second transmission. In this case, since this is the second time, the timing control circuit 8 activates the output 81 and clears the register 9t- in advance. When the second information is stored in the register 9, the timing control circuit 8 activates the output gate and operates the comparator 16. If both pieces of information are the same, the comparator 16 activates the coincidence output 160 and instructs the timing control circuit 8 to continue its operation. Similar operations occur when receiving information from the third time onwards.
前回までに一致が確認された情報はレジスタ１５に格納
されておシ、−１新たに受信される情報はレジスタ９に
格納される。Information whose coincidence has been confirmed up to the previous time is stored in the register 15, and -1 newly received information is stored in the register 9.
同一情報をＮ回（Ｎは２以上の整数）比較する仕様の場
合であれば、第（Ｎ＋１）回目の情報受信が最終回とな
る。この場合、一致出カ１６０が出力されると、タイミ
ング制御回路８は最終回ということで出力８４ヲ活性化
し、その結果、該情報を受信側情報処理システム１７へ
転送することができる。In the case of a specification in which the same information is compared N times (N is an integer of 2 or more), the (N+1)th time of information reception is the final time. In this case, when the coincidence output 160 is output, the timing control circuit 8 activates the output 84 because it is the final time, and as a result, the information can be transferred to the receiving side information processing system 17.
これに対し、送信側情報処理システム１が故障すれば、
アドレスバスおよびデータバス２．３よシ異常な情報が
送られてくる。従って、前回までに受信した情報と異な
るため、比較器１６は不一致出力１６１を活性化する。On the other hand, if the transmitting side information processing system 1 fails,
Abnormal information is sent through the address bus and data bus 2.3. Therefore, since the information is different from the previously received information, the comparator 16 activates the mismatch output 161.
その結果、タイミング制御回路８はただちにすべてのレ
ジスタ６．９．１５をクリアするとともに異常情報を受
信側情報処理システム１７へ送出することを防止する。As a result, the timing control circuit 8 immediately clears all registers 6.9.15 and prevents the abnormal information from being sent to the receiving information processing system 17.
また、第１回目の受信情報がすでに異常である場合は、
すでに送信側情報処理システム１が故障している場合で
あるから、同一内容の情報を今後複数回連続して送出す
ることは不可能であり、この場合も異常情報を受信側情
報処理システム１ケへ送出することを防止することがで
きる。Also, if the first received information is already abnormal,
Since this is a case where the sending side information processing system 1 has already failed, it is impossible to send the same information multiple times in succession in the future, and in this case as well, the abnormal information is transmitted to the receiving side information processing system 1. can be prevented from being sent to.
すなわち、本実施例においては、送信側情報処環システ
ムｌから受信側情報処理システム１７あてに、あらかじ
め定めた複数回連続して送られる同一内容の情報を、た
とえば受信回路４．５で受信し、レジスタ６．９．１５
で格納する手段と、受信した複数個の情報がすべて同一
か否かを、たとえば論理積回路１１ 、１２および比較
器１６などによシ確認する手段と、受信した複数個の情
報がすべて同一であることを、たとえば論理積回路１３
の出力１３０によシ確認したときのみ受信側情報処理シ
ステム１７に情報を論理積回路１４を介して転送する手
段を備え、送信側情報処理システムｌから受信側情報処
理システム１７に制御情報の転送を行っている。That is, in this embodiment, for example, the receiving circuit 4.5 receives information with the same content that is successively sent a predetermined number of times from the transmitting information processing system l to the receiving information processing system 17. , register 6.9.15
and a means for checking whether the received plural pieces of information are all the same using, for example, AND circuits 11 and 12 and the comparator 16, and a means for checking whether the received plural pieces of information are all the same. For example, the AND circuit 13
The control information is transferred from the transmitting side information processing system l to the receiving side information processing system 17 only when the output 130 of the transmitting side information processing system l is confirmed. It is carried out.
なお、送信側情報処理システム１セよび受信側情報処理
システム１７は、中央制御装置、記憶装置、データチャ
ネル装置等から構成されておシ、公知の技術にて実現で
きるため説明は省略する。また、タイミング制御回路色
は、通常の論理回路設計技術者が容易に設計できるもの
で、とくに説明は省略する。Note that the transmitting side information processing system 1 and the receiving side information processing system 17 are composed of a central control unit, a storage device, a data channel device, etc., and can be realized using known techniques, so a description thereof will be omitted. Further, the timing control circuit colors can be easily designed by an ordinary logic circuit design engineer, and a special explanation thereof will be omitted.
上記説明では、情報の流れは一方向と仮定したが、情報
通信は一般的には双方向で実施される。In the above description, it is assumed that the flow of information is unidirectional, but information communication is generally performed bidirectionally.
従って、上記説明した回路を逆方向の情報に対しても設
けることによシ双方向の情報通信に本発明を適用するこ
とができる。Therefore, by providing the circuit described above also for information in the opposite direction, the present invention can be applied to bidirectional information communication.
以上のような構成となっているため、情報を送出する側
の情報処理システムが故障しても、異常な情報によシ、
情報を受信する側の情報処理システムがじょう乱を受け
ることを防止できる。With the above configuration, even if the information processing system that sends the information fails, abnormal information will not be used.
It is possible to prevent the information processing system on the side that receives information from being disturbed.
発明の詳細
な説明したように、本発明によれば、情報を送出する側
の情報処理システムの故障もしくはソフトウェアの暴走
によシ異常な情報が送出された場合でも、異常情報の転
送をただちに抑止することが可能となυ、情報を受信す
る側の情報処理システムのしよう乱を防止することがで
きる。As described in detail, according to the present invention, even if abnormal information is sent due to a failure of the information processing system on the information sending side or runaway of software, the transfer of the abnormal information can be immediately inhibited. This makes it possible to prevent disturbances to the information processing system on the receiving side.
図は本発明の一実施例である。
１・・・送信側情報処理システム、２・・・アドレスノ
くス、３・・・データバス、４，５・・・受信回路、６
，９゜１５・・・レジスタ、７・・・装置番号照合回路
、８・・・タイミンク制御回路、１０ 、１１．１２
、１３ 、１４・・・論理積回路、１６・・・比較器、
１７・・・受信側情報処理システム、７０・・・装置番
号照合回路７の出力、（資）、 ８１ 、８２ 、８３
、８４ 、８５・・・タイミング制御回路８の出力、
９０・・・レジスタ９の出力、１３０・・・論理積回路
１３の出力、１４０・・・論理積回路１４の出力、１５
０・・・レジスタ１５の出力、１６０・・・比較器１６
の一致出力、１６１・・・比較器１６の不一致出力。
特許出願人 日本電信電話公社The figure shows one embodiment of the invention. 1... Sending side information processing system, 2... Address node, 3... Data bus, 4, 5... Receiving circuit, 6
,9゜15...Register, 7...Device number verification circuit, 8...Timing control circuit, 10, 11.12
, 13, 14... AND circuit, 16... Comparator,
17... Receiving side information processing system, 70... Output of device number verification circuit 7, (capital), 81, 82, 83
, 84, 85...output of the timing control circuit 8,
90... Output of register 9, 130... Output of AND circuit 13, 140... Output of AND circuit 14, 15
0... Output of register 15, 160... Comparator 16
161 . . . non-coincidence output of the comparator 16. Patent applicant Nippon Telegraph and Telephone Corporation
Claims (1)
情報転送方式において、前記二つの情報処理システム間
に、該二つの情報処理システムの−１の情報処理システ
ムから他方の情報処理システムあてに、あらかじめ定め
た複数回連続して送出される同一内容の情報を受信し格
納する手段と、該受信した複数個の情報がすべて同一か
否か′ｆ、確認する手段と、該確認する手段によシ該受
信した複数個の情報がすべて同一であることを確認した
ときのみ該他方の情報処理システムあてに該情報を転送
する手段とを備えてなる制御情報転送方式。In a control information transfer method between two information processing systems that communicate information with each other, between the two information processing systems, from the -1 information processing system of the two information processing systems to the other information processing system, means for receiving and storing information of the same content that is successively transmitted a plurality of predetermined times; a means for checking whether or not all the received pieces of information are the same; 2. A control information transfer method, comprising: means for transferring the information to the other information processing system only when it is confirmed that the plural pieces of information received are all the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58074834A JPS59200365A (en) | 1983-04-27 | 1983-04-27 | Transfer system of control information |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58074834A JPS59200365A (en) | 1983-04-27 | 1983-04-27 | Transfer system of control information |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59200365A true JPS59200365A (en) | 1984-11-13 |
Family
ID=13558759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58074834A Pending JPS59200365A (en) | 1983-04-27 | 1983-04-27 | Transfer system of control information |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59200365A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2420431A (en) * | 2004-11-19 | 2006-05-24 | Fisher Rosemount Systems Inc | Secure data writing system for use in safety instrumented process control systems |
| JP2007257386A (en) * | 2006-03-24 | 2007-10-04 | Mitsubishi Motors Corp | Method and system for verifying data for vehicle electronic controller |
| GB2449370A (en) * | 2004-11-19 | 2008-11-19 | Fisher Rosemount Systems Inc | Generating a script to perform a secure write with user confirmation in process control systems |
-
1983
- 1983-04-27 JP JP58074834A patent/JPS59200365A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2420431A (en) * | 2004-11-19 | 2006-05-24 | Fisher Rosemount Systems Inc | Secure data writing system for use in safety instrumented process control systems |
| GB2420431B (en) * | 2004-11-19 | 2008-10-29 | Fisher Rosemount Systems Inc | Secure data write apparatus and methods for use in safety instrumented process control systems |
| GB2449370A (en) * | 2004-11-19 | 2008-11-19 | Fisher Rosemount Systems Inc | Generating a script to perform a secure write with user confirmation in process control systems |
| CN102591199A (en) * | 2004-11-19 | 2012-07-18 | 费舍-柔斯芒特系统股份有限公司 | Secure data write apparatus and methods for use in safety instrumented process control systems |
| US8233998B2 (en) | 2004-11-19 | 2012-07-31 | Fisher-Rosemount Systems, Inc. | Secure data write apparatus and methods for use in safety instrumented process control systems |
| JP2007257386A (en) * | 2006-03-24 | 2007-10-04 | Mitsubishi Motors Corp | Method and system for verifying data for vehicle electronic controller |
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