JPH02189665A - Bus system - Google Patents
Bus systemInfo
- Publication number
- JPH02189665A JPH02189665A JP1055389A JP1055389A JPH02189665A JP H02189665 A JPH02189665 A JP H02189665A JP 1055389 A JP1055389 A JP 1055389A JP 1055389 A JP1055389 A JP 1055389A JP H02189665 A JPH02189665 A JP H02189665A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- data
- bit
- error
- generated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To transfer data after correcting an one-bit error generated on a bus and to continue the operation of a system even when the one-bit fault is generated in the bus by adding an ECC bit to the bus.
CONSTITUTION: Devices 2, 3 connected to the bus 1 with (n + m) bit width output the data of (n + m) bits obtained by adding an ECC bit consisting of m bits to data consisting of n bits at the time of outputting the data to the bus 1 through an ECC forming circuit 4. In the case of inputting data from the bus 1, the data of (n + m) bits are inputted, and when an one-bit error is generated, the error is corrected by an ECC checking circuit 5 and the corrected data of n bits are outputted. In the case of a 2-bit error, the error is regarded as an incorrigible error. Consequently, data transfer can be attained even when an one-bit error is generated on the bus, and operation of the system can be continued even when an one-bit fault is generated on the bus.
COPYRIGHT: (C)1990,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1055389A JPH02189665A (en) | 1989-01-18 | 1989-01-18 | Bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1055389A JPH02189665A (en) | 1989-01-18 | 1989-01-18 | Bus system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02189665A true JPH02189665A (en) | 1990-07-25 |
Family
ID=11753446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1055389A Pending JPH02189665A (en) | 1989-01-18 | 1989-01-18 | Bus system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02189665A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015507812A (en) * | 2011-12-23 | 2015-03-12 | インテル・コーポレーション | Self-healing logic for stacked memory architectures |
-
1989
- 1989-01-18 JP JP1055389A patent/JPH02189665A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015507812A (en) * | 2011-12-23 | 2015-03-12 | インテル・コーポレーション | Self-healing logic for stacked memory architectures |
| US9646720B2 (en) | 2011-12-23 | 2017-05-09 | Intel Corporation | Self-repair logic for stacked memory architecture |
| US10224115B2 (en) | 2011-12-23 | 2019-03-05 | Intel Corporation | Self-repair logic for stacked memory architecture |
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