JPH02189665A - Bus system - Google Patents

Bus system

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Publication number
JPH02189665A
JPH02189665A JP1055389A JP1055389A JPH02189665A JP H02189665 A JPH02189665 A JP H02189665A JP 1055389 A JP1055389 A JP 1055389A JP 1055389 A JP1055389 A JP 1055389A JP H02189665 A JPH02189665 A JP H02189665A
Authority
JP
Japan
Prior art keywords
bus
data
bit
bits
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1055389A
Other languages
Japanese (ja)
Inventor
Makoto Ogiwara
誠 荻原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1055389A priority Critical patent/JPH02189665A/en
Publication of JPH02189665A publication Critical patent/JPH02189665A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To transfer data after correcting an one-bit error generated on a bus and to continue the operation of a system even when the one-bit fault is generated in the bus by adding an ECC bit to the bus. CONSTITUTION:Devices 2, 3 connected to the bus 1 with (n + m) bit width output the data of (n + m) bits obtained by adding an ECC bit consisting of m bits to data consisting of n bits at the time of outputting the data to the bus 1 through an ECC forming circuit 4. In the case of inputting data from the bus 1, the data of (n + m) bits are inputted, and when an one-bit error is generated, the error is corrected by an ECC checking circuit 5 and the corrected data of n bits are outputted. In the case of a 2-bit error, the error is regarded as an incorrigible error. Consequently, data transfer can be attained even when an one-bit error is generated on the bus, and operation of the system can be continued even when an one-bit fault is generated on the bus.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はバス方式に関し、情報処理装置等のデータ転送
用バスに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus system, and more particularly to a data transfer bus for information processing devices and the like.

〔従来の技術〕[Conventional technology]

従来、この種のバスには、8ビット単位に奇数、又は、
偶数パリティビットを用いて1ビツトエラーの検出のみ
を行っていた。
Conventionally, this type of bus has an odd number of 8 bits, or
Only one bit error was detected using even parity bits.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

近年、データ転送の大容量化にともない、バスのビット
数(以降幅)も多くなって来ている。
In recent years, as data transfer capacity has increased, the number of bits (hereinafter referred to as width) of buses has also increased.

上述した従来のパリティ方式では、障害の検出のみを行
うもので、データ転送を実行し直さなければならず、又
、バスの1ビツトが故障の場合、システムの運用が続行
できないという欠点があった。
The above-mentioned conventional parity method only detects failures and requires re-execution of data transfer, and also has the disadvantage that system operation cannot be continued if one bit of the bus fails. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明のバス方式の構成は、情報処理装置等のデータ転
送用バスにおいて、そのバスの転送データのデータ部n
ビットと、そのnビットのデータに対するECCのmビ
ットとの総計(n+m)ビットのビット幅で構成された
バスを有することを特徴とする。
The configuration of the bus system of the present invention is such that in a data transfer bus of an information processing device, the data portion n of the transfer data of the bus is
It is characterized by having a bus configured with a total bit width of (n+m) bits, including bits and m bits of ECC for the n bits of data.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

(n 十m )ビット幅のバス1に接続された装置2及
び3は、バスにデータを出力する時点で、ECC作成回
路4によりnビットのデータにmビットのECCビット
を付加した(n+m)ビットのデータをバスへ出力し、
バスからデータを入力する場合には、(n+m)ビット
のデータバスを入力とし、ECCチエツク回路5により
、1とットエラーの時は、訂正し、その訂正したnビッ
トのデータを出力する。2とットエラーの時は、訂正不
能エラーとする。
When devices 2 and 3 connected to bus 1 with a width of (n 10m) bits output data to the bus, the ECC creation circuit 4 adds m ECC bits to n bits of data (n+m). Outputs bit data to the bus,
When inputting data from a bus, an (n+m) bit data bus is input, and an ECC check circuit 5 corrects any 1-bit errors, and outputs the corrected n-bit data. 2. If it is a hit error, it is considered an uncorrectable error.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、バスにECCビットを付
加することにより、バス上で1とットエラーが発生して
も訂正できるのでデータ転送を行うことができ、又バス
が1ビツト故障しても、システムの運用の続行が可能と
なり、高信頼度のシステムが構成できる効果がある。
As explained above, in the present invention, by adding an ECC bit to the bus, even if a 1-bit error occurs on the bus, it can be corrected, so data transfer can be performed. , it is possible to continue operating the system, and a highly reliable system can be configured.

る。Ru.

1・・・・・・(n + m >ビット幅の)くス、2
,3・・・・・・装置、4・・・・・・ECC作成回路
、5・・・・・・ECCチエツク回路。
1...(n + m > bit width), 2
, 3... device, 4... ECC creation circuit, 5... ECC check circuit.

Claims (1)

【特許請求の範囲】[Claims] 情報処理装置等のデータ転送用バスにおいて、そのバス
の転送データのデータ部nビットと、そのnビットのデ
ータに対するECCのmビットとの総計(n+m)ビッ
トのビット幅で構成されたバスを有することを特徴とす
るバス方式。
A data transfer bus for an information processing device, etc., which has a total bit width of (n+m) bits, consisting of n bits of data in the transfer data of the bus and m bits of ECC for the n bits of data. This bus system is characterized by:
JP1055389A 1989-01-18 1989-01-18 Bus system Pending JPH02189665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1055389A JPH02189665A (en) 1989-01-18 1989-01-18 Bus system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1055389A JPH02189665A (en) 1989-01-18 1989-01-18 Bus system

Publications (1)

Publication Number Publication Date
JPH02189665A true JPH02189665A (en) 1990-07-25

Family

ID=11753446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1055389A Pending JPH02189665A (en) 1989-01-18 1989-01-18 Bus system

Country Status (1)

Country Link
JP (1) JPH02189665A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015507812A (en) * 2011-12-23 2015-03-12 インテル・コーポレーション Self-healing logic for stacked memory architectures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015507812A (en) * 2011-12-23 2015-03-12 インテル・コーポレーション Self-healing logic for stacked memory architectures
US9646720B2 (en) 2011-12-23 2017-05-09 Intel Corporation Self-repair logic for stacked memory architecture
US10224115B2 (en) 2011-12-23 2019-03-05 Intel Corporation Self-repair logic for stacked memory architecture

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