JPH02189665A - Bus system - Google Patents

Abstract

PURPOSE:To transfer data after correcting an one-bit error generated on a bus and to continue the operation of a system even when the one-bit fault is generated in the bus by adding an ECC bit to the bus. CONSTITUTION:Devices 2, 3 connected to the bus 1 with (n + m) bit width output the data of (n + m) bits obtained by adding an ECC bit consisting of m bits to data consisting of n bits at the time of outputting the data to the bus 1 through an ECC forming circuit 4. In the case of inputting data from the bus 1, the data of (n + m) bits are inputted, and when an one-bit error is generated, the error is corrected by an ECC checking circuit 5 and the corrected data of n bits are outputted. In the case of a 2-bit error, the error is regarded as an incorrigible error. Consequently, data transfer can be attained even when an one-bit error is generated on the bus, and operation of the system can be continued even when an one-bit fault is generated on the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus system, and more particularly to a data transfer bus for information processing devices and the like.

[Conventional technology]

Conventionally, this type of bus has an odd number of 8 bits, or
Only one bit error was detected using even parity bits.

[Problem to be solved by the invention]

In recent years, as data transfer capacity has increased, the number of bits (hereinafter referred to as width) of buses has also increased.

The above-mentioned conventional parity method only detects failures and requires re-execution of data transfer, and also has the disadvantage that system operation cannot be continued if one bit of the bus fails. .

[Means to solve the problem]

The configuration of the bus system of the present invention is such that in a data transfer bus of an information processing device, the data portion n of the transfer data of the bus is
It is characterized by having a bus configured with a total bit width of (n+m) bits, including bits and m bits of ECC for the n bits of data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

When devices 2 and 3 connected to bus 1 with a width of (n 10m) bits output data to the bus, the ECC creation circuit 4 adds m ECC bits to n bits of data (n+m). Outputs bit data to the bus,
When inputting data from a bus, an (n+m) bit data bus is input, and an ECC check circuit 5 corrects any 1-bit errors, and outputs the corrected n-bit data. 2. If it is a hit error, it is considered an uncorrectable error.

〔Effect of the invention〕

As explained above, in the present invention, by adding an ECC bit to the bus, even if a 1-bit error occurs on the bus, it can be corrected, so data transfer can be performed. , it is possible to continue operating the system, and a highly reliable system can be configured.

Ru.

1...(n + m > bit width), 2
, 3... device, 4... ECC creation circuit, 5... ECC check circuit.

Claims (1)

[Claims] A data transfer bus for an information processing device, etc., which has a total bit width of (n+m) bits, consisting of n bits of data in the transfer data of the bus and m bits of ECC for the n bits of data. This bus system is characterized by: