JPH0897803A - Data transmission system - Google Patents

Abstract

PURPOSE: To prevent malfunctions in a reception part at the time of the transmission/reception control of data through a buffer memory. CONSTITUTION: A transmission part is provided with a parity check circuit 10 and a logical data conversion circuit 11 and the parity check of a transmission buffer memory 1 is performed. When a parity error is present, signals inside a transmission frame are converted in the logical data conversion circuit 11, a transmission frame format is changed to an erroneous format, the frame is cancelled as a CRC error on a reception part side and the data contents of the erroneous frame are prevented from being transmitted to the reception part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication processing device for controlling transmission / reception of data via a buffer memory, and to a data transmission system.

[0002]

2. Description of the Related Art Conventionally, a data communication processing device for transmitting and receiving digital data via a transmission line is required to have high reliability.

In a conventional data transmission apparatus, a CRC (Cy) is used to detect a code error occurring in a transmission line.
CLICK Redundancy Check) method,
A parity check method is used. Further, there is one that has a function of performing error detection for a code error in the transmission buffer memory by adding an error detection code such as a parity check code to a transmission frame (for example,
(See Japanese Patent Publication No. 62-37581).

4 and 5 show a conventional data transmission method. FIG. 4 shows a typical configuration example of the transmission / reception control unit. FIG. 5 shows a frame configuration example.

Referring to FIGS. 4 and 5, on the transmission side, transmission data is written from transmission control section 24 into transmission buffer memory 1. At that time, the block check code 17 generated in the block check code generation circuit 2 is simultaneously written.

The data sequentially read from the transmission buffer memory 1 is sent to the transmission frame generation circuit 3 with a start code 15, a data 16 and a block check code 1.
7, the CRC 18, and the end code 19 are added to form the frame format shown in FIG.

In the receiving section, the signal transmitted through the transmission path is passed through the modem 5 and is received by the received frame detection circuit 6 by the C signal.
The RC 18 is checked for correctness and the data 16 is written in the reception buffer memory 7. Whether or not there is a transmission path error checked by the reception frame detection circuit 6 is notified to the reception processing unit 25 as a transmission error detection signal 13.

On the other hand, when the data written in the buffer memory 7 is read by a reception processing unit (not shown), the value generated by the block check code detection circuit 8 and the presence / absence of an error in the buffer memory 7 in the frame are checked. The detection result is notified to the reception processing unit 25 as the memory error detection signal 12.

[0009]

However, according to the conventional data transmission method, in order to detect an error occurring in the transmission buffer memory 1 and the reception buffer memory 7 in the control circuit, the transmission unit side and the reception unit side have to detect each other. It was necessary to add hardware for buffer memory error detection to both.

Further, when the buffer memory error detection signal is output to the receiving unit side, it is necessary to add a function (software) for taking measures such as discarding the received erroneous data, which makes the processing complicated. Was becoming.

Therefore, an object of the present invention is to prevent the data content of an erroneous frame from being transmitted to the receiving section when the content of the transmission buffer memory is erroneous at the time of data transmission in the digital transmission device, and to prevent the receiving section from transmitting. It is to provide a data transmission method that prevents erroneous operation that can be performed.

[0012]

According to the present invention, in a data transmission system for transmitting and receiving data via a transmission line, a parity code is generated at the time when the transmission data is written in the transmission buffer memory on the transmission unit side. And a parity check circuit for checking the parity code generated from the transmission data sent from the transmission buffer memory to the transmission frame generation circuit, and the parity check circuit when a parity error is detected. When a parity error detection signal output from the input terminal is input, a logical data conversion circuit that converts the logical data in the transmission frame input from the transmission frame generation circuit and outputs it to the modem is characterized. The following data transmission method can be obtained.

[0013]

In the data transmission system of the present invention, when the parity error detection signal from the parity check circuit is input to the logical data conversion circuit when a parity error is detected, the transmission frame input from the transmission frame generation circuit is input. The logical data in the inside is converted and output from the logical data conversion circuit to the modem.

The transmission data sequentially read from the transmission buffer memory is subjected to a parity check by a parity check circuit to detect an error in the transmission buffer memory.

When an error is detected in the transmission buffer memory, a parity error detection signal is notified to the logical data conversion circuit, and when the parity error detection signal is input to the logical data conversion circuit, it is generated by the transmission frame generation circuit. Logically inverts the contents of the frame being rendered.

[0016]

1 and 2 show an embodiment of a data transmission system of the present invention. FIG. 1 shows a block configuration diagram of the transmission / reception control unit, and FIG. 2 shows an example of a frame configuration output from the logical data conversion circuit 11 to the modem 4 when there is no error in the transmission buffer memory 1. In FIGS. 1 and 1, the same parts as those in FIGS. 4 and 5 will be described with the same reference numerals.

Referring to FIGS. 1 and 2, in the data transmission system of the present invention, a transmission control section 24, a transmission buffer memory 1 for writing transmission data from the transmission control section 24, and a transmission buffer are provided on the transmission section side. A parity code generation circuit 9 that generates a parity generated from the transmission data when the transmission data is written to the memory 1, a parity check circuit 10 that confirms whether the parity code sent to the transmission frame generation circuit 3 is correct, and a parity check circuit. A logical data conversion circuit 11 for converting the logical data output from the transmission frame generation circuit 3 to the modem 4 based on the parity error detection signal 14 output from 10 is provided.

Further, on the receiving side, the received frame detection circuit 6 for confirming whether the signal received via the transmission line is a correct frame via the modem 5 and, if it is a correct frame, the CRC 18 is checked. After the confirmation, the reception buffer memory 7 for writing the received data, and the reception processing unit 25 for passing the reception data written in the reception buffer memory 7 are provided.

On the transmitter side, the transmission data is written from the transmission controller 24 into the transmission buffer memory 1. The parity code generation circuit 9 generates a parity generated from the transmission data when the transmission data is written in the transmission buffer memory 1. The parity check circuit 10 confirms whether the parity code sent to the transmission frame generation circuit 3 is correct. The logical data conversion circuit 11 converts the logical data output from the transmission frame generation circuit 3 to the modem 4 based on the parity error detection signal 14 output from the parity check circuit 10.

On the transmitting unit side, transmission data is written from the transmission control unit 24 to the transmission buffer memory 1 by adding a parity bit from the parity code generating circuit 9 every 8 bits. The parity check circuit 10 performs a parity check on the transmission data sequentially read from the transmission buffer memory 1, and detects an error in the transmission buffer memory 1.

If an error is detected in the transmission buffer memory 1, the logic data conversion circuit 11 is notified of the parity error detection signal 14. When the parity error detection signal 14 is input to the logical data conversion circuit 11,
The contents of the frame generated by the transmission frame generation circuit 3 are logically inverted.

Therefore, the start code 15, data 16, CRC 18, and end code 19 are also logically inverted and sent to the modem 4 as an incorrect frame. If there is no error in the transmission buffer memory 1, the frame generated by the transmission frame generation circuit 3 is sent to the modem 4 as a correct frame.

On the receiving side, the signal received via the transmission line is checked by the received frame detection circuit 6 via the modem 5 to see if it is a correct frame, and if it is a correct frame, the CRC 18 is checked for correctness. After confirmation, the received data 16 is written in the reception buffer memory 7. next,
The reception data written in the reception buffer memory 7 is passed to the reception processing unit 25.

FIG. 3 is a diagram showing an example of a frame structure output from the logical data conversion circuit 11 to the modem 4 when a parity error occurs in the transmission buffer memory 1 in the data transmission system of the present invention.

If a parity error occurs in the transmission buffer memory 1, the start code 15, data 16, CRC 18 and end code 19 contained in the transmission frame are logically inverted by the logical data conversion circuit 11 to cause an error. The frame format is output to the modem 4. That is, start code 15, data 1
6, the CRC 18 and the end code 19 are output to the modem 4 as the start code 20 converted into logical data, the data 21 converted into logical data, the CRC 22 converted into logical data, and the end code 23 converted into logical data. It

When an erroneous frame is input to the reception frame detection circuit 6 of the receiving section, it is not recognized as a frame, so that erroneous data is not written in the reception buffer memory 7 and the transmission error detection signal 13 is transmitted from the reception frame detection circuit 6. Is output.

[0027]

As described above, according to the data transmission method of the present invention, the parity check circuit 10 is provided on the transmitter side and has the error detection function of the transmission buffer memory 1. If an error is detected, Transforms the transmitted frame,
Since the star, code, data, CRC, and end code in the frame are mistaken, C
It is recognized as an RC error or frame error, and it is not recognized that a normal frame has been received and the frame is discarded. Therefore, a special hardware for checking whether the content of the frame received by the receiving side is incorrect or not. There is no need to add software or software.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transmission system of the present invention.

FIG. 2 is a configuration diagram of a frame output from the logical data conversion circuit of FIG. 1 to a modem.

FIG. 3 is a configuration diagram of a frame output from the logical data conversion circuit to the modem when a parity error occurs in the transmission buffer memory in the data transmission system of the present invention.

FIG. 4 is a block diagram showing a typical configuration example of a transmission / reception control unit.

5 is a block diagram of the frame of FIG. 4. FIG.

[Explanation of symbols]

 1 transmission buffer memory 2 block check generation circuit 3 transmission frame generation circuit 4, 5 modem 6 reception frame detection circuit 7 reception buffer memory 8 block check code detection circuit 9 parity code generation circuit 10 parity check circuit 11 logical data conversion circuit 12 memory error Detection signal 13 Transmission error detection signal 14 Parity error detection signal 15 Start code 16 Data 17 Block check code 18 CRC 19 End code 20 Logical data converted start code 21 Logical data converted data 22 Logical data converted CRC 23 End code converted into logical data 24 Transmission control unit 25 Reception processing unit

Claims (4)

[Claims] 1. A parity code generation circuit for generating a parity code when transmission data is written in a transmission buffer memory of a transmitter in a data transmission method for transmitting and receiving data via a transmission line, and the transmission buffer. A parity check circuit for checking the parity code generated from the transmission data sent from the memory to the transmission frame generation circuit, and a parity error detection signal output from the parity check circuit when a parity error is detected is input. A data transmission system characterized by having a logical data conversion circuit for converting the logical data in the transmission frame input from the transmission frame generation circuit and outputting it to the modem when the transmission is performed. 2. A data transmission method for transmitting and receiving data via a transmission line, a transmission control unit, a transmission buffer memory for writing transmission data from the transmission control unit, and the transmission data for writing in the transmission buffer memory. A parity code generation circuit that generates a parity generated from the transmission data at a time point, a parity check circuit that confirms whether the parity code sent to the transmission frame generation circuit is correct, and a parity error detection signal that is output from the parity check circuit. A logical data conversion circuit for converting the logical data output from the transmission frame generation circuit to the modem based on the above, and further, the signal received through the transmission path on the receiving side is a correct frame via the modem. Received frame detection circuit to check whether or not, and if the frame is correct A data transmission method comprising a reception buffer memory for writing received data after confirming whether the CRC is correct or incorrect, and a reception processing unit for passing the reception data written in the reception buffer memory. 3. The data transmission method according to claim 1, wherein the transmission data sequentially read from the transmission buffer memory is subjected to a parity check by the parity check circuit to eliminate an error in the transmission buffer memory. A data transmission method characterized by detecting. 4. The data transmission method according to claim 1, wherein when an error is detected in the transmission buffer memory, a parity error detection signal is notified to the logical data conversion circuit, and the logical data conversion circuit is notified. When the parity error detection signal is input to the data transmission system, the contents of the frame generated by the transmission frame generation circuit are logically inverted.