JPS6237581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data communication processing device that controls data transmission and reception via a buffer memory.
The present invention relates to a data transmission method that can improve reliability.

A data communication processing device that transmits and receives digital data via a transmission path is required to have extremely high reliability. Conventional data communication processing equipment uses a parity check method,
CRC (Cyclic Redundancy Check) methods are already widely used.

FIG. 1 is a diagram showing a conventional data transmission system. In the figure, a is a block diagram showing a typical configuration example of a transmission/reception control section, and b is a diagram showing an example frame configuration.

On the transmission side, transmission data is written to a transmission buffer memory 1 from a transmission processing section (not shown) and then sequentially read out, and then sent to a parallel-to-serial conversion section (P/S) 2.
is converted into a serial signal at . After the converted serial signal, the CRC generation circuit 3 generates the
A CRC code is added to form a frame (FIG. 1b), and the frame is sent out to the transmission path via the transmission drive circuit 4.

On the receiving side, the signal transmitted via the transmission path passes through the receiving buffer 5 and is sent to the serial/parallel converter (S/
After being converted into a parallel signal and written to the reception buffer memory 7 in P) 6, it is read out and passed to a reception processing section (not shown). On the other hand, the CPC detection circuit 8 detects the CRC code, determines the presence or absence of a transmission path error, and notifies the reception processing section using a transmission error detection bit.

However, code errors occur not only on the transmission path;
This problem may also occur in the buffer memory in the control circuit. In particular, as communication capacity gradually increases and frame lengths become longer, and the scale of buffer memory that occupies the control circuit cannot be ignored, sufficient reliability cannot be achieved unless error detection is performed not only for transmission path errors but also for buffer memory. It will not be possible to secure the However, error detection for the buffer memory in the transmission/reception control circuit has not been particularly actively performed.

The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to perform error detection on a buffer memory provided in a data transmission/reception control circuit by transmitting an error detection code such as a parity check code. The purpose is to improve the reliability of data transmission by adding it to the frame. In order to achieve this purpose, in the data transmission system of the present invention, the transmission control section is equipped with a transmission buffer memory for writing and reading transmission data,
In a data transmission processing device that includes a reception buffer memory for writing and reading received data in the reception control unit and transmits and receives data via a transmission path, the transmission control unit generates a check code from an input signal to the transmission buffer memory. The block check code detection circuit detects a check code from the output signal of the reception buffer memory and detects a code error in the received signal in the reception control section, and the block check code generation circuit generates the block check code on the transmitting side. The received block check code is written and read out together with the transmission data in the transmission buffer memory, and a code is generated and added for error detection using the output signal of the transmission buffer memory, and the frame is transmitted. After detecting errors in the received signal using the error detection code, a block check code is generated when reading the received data written in the receive buffer memory, and is compared with the transmitted block check code in the received frame to transmit and It is characterized by detecting errors in the reception buffer memory.

Examples will be described below.

FIG. 2 is a diagram showing an embodiment of the data transmission system of the present invention. In the figure, a shows an example of the configuration of a transmission/reception control section, and b shows an example of the frame structure. In FIG. 2, the same parts as in FIG. 1 are designated by the same numbers, 10 is a block check code generation circuit, and 11 is a buffer memory check code detection circuit.

On the transmitting side, transmission data is written into the transmission buffer memory 1 from a transmission processing section (not shown). At this time, a block check code generation circuit 10 generates a block check code in units of words. The generated block check code is written to the final address of the data after one frame of transmission data has been written to the transmission buffer memory 1. The data sequentially read from the transmission buffer memory 1 is sent to the parallel/serial converter (P/
S) Converted into a serial signal in step 2. After the converted serial signal, a CRC code generated by the CRC generation circuit 3 is added to form a frame (FIG. 2b), and the frame is sent to the transmission line via the transmission drive circuit 4.

On the receiving side, the signal transmitted via the transmission path passes through the receiving buffer 5 and is sent to the serial/parallel converter (S/
P) 6, the signal is converted into a word-by-word parallel signal and written into the reception buffer memory 7. CRC
The detection circuit 8 detects the CRC code added to the frame, determines the presence or absence of a transmission path error, and notifies the error detection result to a reception processing section (not shown).

On the other hand, the data written in the reception buffer memory 7 is read out in word units and passed to the reception processing section. At this time, the block check code detection circuit 11 performs a block counter to generate a block check code, and A comparison is made with the block check code in the frame to detect an error in the buffer memory of the transmission/reception control circuit, and the result is notified to the reception processing section.

FIG. 3 is a diagram showing an embodiment of the block check code generation method in the data transmission system of the present invention. Data #1, #2, . . . , #n consisting of n words and m bits are written word by word to addresses #0, #1, . . . , #(n-1), respectively. At this time, an even or odd parity in the vertical direction is determined for each bit of each word, and a block check code consisting of m bits is generated and added to address #n.

In this way, in the data transmission system of the present invention, it is possible to know errors that have occurred in the transmission path by checking the CRC code, and even if no error has occurred in the transmission path, it is possible to detect errors that have occurred in the transmission/reception control section. This can be determined by checking the block check code.

Among failures in the transmission/reception control section, the transmission buffer memory and reception buffer memory have the highest probability of failure occurrence, and the longer the frame length, the more failures occur. Therefore, it is necessary to constantly dynamically perform and monitor error detection during data writing and reading in the transmission buffer memory, and error detection during data writing and reading in the receiving buffer memory. In the data transmission system of the present invention, when data is output to the reception processing section, error detection is performed regarding the transmission buffer memory and the reception buffer memory, and the result is recognized.

In the embodiment shown in FIG. 2, the block check code generation circuit and the block check code detection circuit are realized by hardware, but in other embodiments, they may be realized by software. It is also possible to realize this. In this case, the software of the transmission processing section counts block check codes in units of words and sends the generated results to the transmission buffer memory. In addition, in the software of the reception processing section, errors in the memory can be detected by counting blocks while extracting the reception data word by word from the reception buffer memory and comparing it with the block check code in the transmission data. In this case, there is an advantage that the hardware configuration of the transmission/reception control circuit can be made completely the same as that of the conventional system.

In addition, in FIG. 3, as an example of the block check code generation method, a case using a vertical even (odd) parity code has been described, but other embodiments include, for example, a group (block) counting check code system. is possible. In this case as well, the basic implementation method is the same, but there is an advantage that the memory error detection ability is further improved.

As explained above, according to the data transmission method of the present invention, error detection in the transmission path and error detection in the transmission/reception buffer memory can be performed during data transmission/reception, so reliability in data communication can be improved. At the same time, it is possible to separately detect failures in the transmission path and failures in the transmitting/receiving buffer, making it easy to respond to failures, which is extremely effective.

[Brief explanation of the drawing]

Figure 1 shows the conventional data transmission method, Figure 2 shows the conventional data transmission method.
This figure shows an embodiment of the data transmission system of the present invention, and FIG. 3 shows an embodiment of the block check code generation method in the data transmission system of the invention. DESCRIPTION OF SYMBOLS 1... Transmission buffer memory, 2... Parallel-to-serial conversion unit (P/S), 3... CRC generation circuit, 4... Transmission drive circuit, 5... Reception buffer, 6... Serial-to-parallel conversion unit (S/P ), 7... Receive buffer memory, 8
...CRC detection circuit, 10...block check code generation circuit, 11...block check code detection circuit.

Claims (1)

[Claims] 1 In a data transmission processing device that transmits and receives data via a transmission path, the transmission control unit includes a transmission buffer memory for writing and reading out transmission data, and the reception control unit includes a reception buffer memory for writing and reading reception data. It is equipped with a block check code generation circuit that generates a check code from the input signal to the buffer memory, and a block check code detection circuit that detects the check code from the output signal of the reception buffer memory and detects a code error in the received signal in the reception control section. On the transmitting side, the block check code generated by the block check code generation circuit is written and read into the transmitting buffer memory along with the transmitting data, and a code for error detection is generated and added based on the output signal of the transmitting buffer memory. A block check code is used when reading the received data written in the receive buffer memory after it is framed and transmitted, and the receiving side performs error detection in the received signal using the code for error detection in the received signal at the stage before the receive buffer memory. A data transmission system characterized in that errors in transmitting and receiving buffer memories are detected by generating a block check code in a received frame and comparing it with a transmitted block check code in a received frame.