JPS5720049A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS5720049A
JPS5720049A JP9469980A JP9469980A JPS5720049A JP S5720049 A JPS5720049 A JP S5720049A JP 9469980 A JP9469980 A JP 9469980A JP 9469980 A JP9469980 A JP 9469980A JP S5720049 A JPS5720049 A JP S5720049A
Authority
JP
Japan
Prior art keywords
check code
memory
signal
transmission
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9469980A
Other languages
Japanese (ja)
Other versions
JPS6237581B2 (en
Inventor
Masamichi Iwama
Satoru Tsushima
Hidenori Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9469980A priority Critical patent/JPS5720049A/en
Publication of JPS5720049A publication Critical patent/JPS5720049A/en
Publication of JPS6237581B2 publication Critical patent/JPS6237581B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end

Abstract

PURPOSE:To improve the reliability of data transmission by detecting an error regarding a buffer memory provided to a control circuit by adding an error detection code, such as a parity check code, in a transmission frame. CONSTITUTION:When transmitted data from a transmission processing part is written in a transmitting buffer memory 1, a block check code for each word is generated by a block check code generating circuit 10 and written in the final address of the transmitted data after one-frame transmitted data is written in the memory 1. Data read successively from the memory 1 are converted by a parallel- seris conversion part 2 into a series signal, which is transmitted to a transmission line via transmission driving circuit 4 after a parity check code from a CRC generating circuit 3 is added after the signal. The signal from this transmission line is passed through a receiving buffer 5 and converted by a series-parallel conversion part 6 into a parallel signal which corresponds to one word; and a block check code detecting circuit 11 detects an error of the memory 1 and a CRC detecting circuit 8 detects a parity error.
JP9469980A 1980-07-11 1980-07-11 Data transmission system Granted JPS5720049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9469980A JPS5720049A (en) 1980-07-11 1980-07-11 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9469980A JPS5720049A (en) 1980-07-11 1980-07-11 Data transmission system

Publications (2)

Publication Number Publication Date
JPS5720049A true JPS5720049A (en) 1982-02-02
JPS6237581B2 JPS6237581B2 (en) 1987-08-13

Family

ID=14117417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9469980A Granted JPS5720049A (en) 1980-07-11 1980-07-11 Data transmission system

Country Status (1)

Country Link
JP (1) JPS5720049A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103298A (en) * 1984-10-26 1986-05-21 富士ゼロックス株式会社 Controller for copying machine
JPS62141240U (en) * 1986-02-27 1987-09-05
JPH0336846A (en) * 1989-06-23 1991-02-18 American Teleph & Telegr Co <Att> Packet generator including carrier language
JPH04306414A (en) * 1991-01-24 1992-10-29 Toshiba Home Techno Kk Burner controller

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0739268B2 (en) * 1986-01-14 1995-05-01 本田技研工業株式会社 Electric power steering device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130638A (en) * 1973-04-16 1974-12-14
JPS5174540A (en) * 1974-12-25 1976-06-28 Fujitsu Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130638A (en) * 1973-04-16 1974-12-14
JPS5174540A (en) * 1974-12-25 1976-06-28 Fujitsu Ltd

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103298A (en) * 1984-10-26 1986-05-21 富士ゼロックス株式会社 Controller for copying machine
JPS62141240U (en) * 1986-02-27 1987-09-05
JPH0336846A (en) * 1989-06-23 1991-02-18 American Teleph & Telegr Co <Att> Packet generator including carrier language
JPH04306414A (en) * 1991-01-24 1992-10-29 Toshiba Home Techno Kk Burner controller

Also Published As

Publication number Publication date
JPS6237581B2 (en) 1987-08-13

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