JPS5552513A - Pcm signal processor - Google Patents

Pcm signal processor

Info

Publication number
JPS5552513A
JPS5552513A JP12444778A JP12444778A JPS5552513A JP S5552513 A JPS5552513 A JP S5552513A JP 12444778 A JP12444778 A JP 12444778A JP 12444778 A JP12444778 A JP 12444778A JP S5552513 A JPS5552513 A JP S5552513A
Authority
JP
Japan
Prior art keywords
error
circuit
data
signal
gate circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12444778A
Other languages
Japanese (ja)
Inventor
Mitsuharu Tsuchiya
Kanji Odagi
Ryoichi Wada
Takanori Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12444778A priority Critical patent/JPS5552513A/en
Publication of JPS5552513A publication Critical patent/JPS5552513A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the generation of an unpleasant sound due to error detection of error data, by detecting error regenerated data by either one or both of error detecting methods using 1st and 2nd check codes.
CONSTITUTION: When cyclic code CRC circuit 3 detects an error block while an input signal is sequentially written in memory method 1, an ERROR signal from memory method 1 becomes "1" and output DATA is cut off by AND gate circuit 4. Then, correct data, restored by exclusive-OR gate circuit 9, is outputted by way of AND gate circuit 7. Next, when circuit 3 fails to detect the error data, signal ERROR is "0" and through the assignment of memory address controller 2, an error detection signal of a "p" code is obtained as an output signal to gate circuit 9. As a result, AND gate circuit 14 outputs "1" and among AND gate circuits 4, 7 and 11, only circuit 11 generates an output signal. Gate circuit 11 also outputs interpolation data generated by interpolation signal generating circuit 12.
COPYRIGHT: (C)1980,JPO&Japio
JP12444778A 1978-10-09 1978-10-09 Pcm signal processor Pending JPS5552513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12444778A JPS5552513A (en) 1978-10-09 1978-10-09 Pcm signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12444778A JPS5552513A (en) 1978-10-09 1978-10-09 Pcm signal processor

Publications (1)

Publication Number Publication Date
JPS5552513A true JPS5552513A (en) 1980-04-17

Family

ID=14885731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12444778A Pending JPS5552513A (en) 1978-10-09 1978-10-09 Pcm signal processor

Country Status (1)

Country Link
JP (1) JPS5552513A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57131140A (en) * 1980-12-18 1982-08-13 Rca Corp Method and device for correcting digital error

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57131140A (en) * 1980-12-18 1982-08-13 Rca Corp Method and device for correcting digital error
JPH046135B2 (en) * 1980-12-18 1992-02-04 Rca Licensing Corp

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