JPS54103639A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS54103639A
JPS54103639A JP928278A JP928278A JPS54103639A JP S54103639 A JPS54103639 A JP S54103639A JP 928278 A JP928278 A JP 928278A JP 928278 A JP928278 A JP 928278A JP S54103639 A JPS54103639 A JP S54103639A
Authority
JP
Japan
Prior art keywords
data
bit
parity bit
processor
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP928278A
Other languages
Japanese (ja)
Inventor
Kiyoshi Umezawa
Yoshinori Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP928278A priority Critical patent/JPS54103639A/en
Publication of JPS54103639A publication Critical patent/JPS54103639A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To avoid the data process based on the incorrect data by providing the parity bit generator which generates the error correction check bit of before correction of the error which read out the parity bit to be transferred to the processor from the memory element along with the data.
CONSTITUTION: When the parity bit added to the data which transmits the data to data processor 8 from memory unit 1 is grown, unit 1 sends the read-out data bit to processor 8 through data bit error correction circuit 6. At the same time, unit 1 generates the parity bit corresponding to the data bit from parity bit generator 5 via the check bit of error correction check bit memory part 3 to then sent the parity bit to processor 8 via parity bit error correction circuit 7. In this case, if some error is detected for the value read out from data bit memory part 2 or part 8, the error is detected through detector circuit 4 to be sent to circuit 6 and 7. And each data and parity bit are corrected to be sent to processor 8.
COPYRIGHT: (C)1979,JPO&Japio
JP928278A 1978-02-01 1978-02-01 Memory unit Pending JPS54103639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP928278A JPS54103639A (en) 1978-02-01 1978-02-01 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP928278A JPS54103639A (en) 1978-02-01 1978-02-01 Memory unit

Publications (1)

Publication Number Publication Date
JPS54103639A true JPS54103639A (en) 1979-08-15

Family

ID=11716109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP928278A Pending JPS54103639A (en) 1978-02-01 1978-02-01 Memory unit

Country Status (1)

Country Link
JP (1) JPS54103639A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968899A (en) * 1982-10-13 1984-04-18 Nec Corp Parity producing system of memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968899A (en) * 1982-10-13 1984-04-18 Nec Corp Parity producing system of memory device

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