JPS5562579A - Control system of buffer memory unit - Google Patents

Control system of buffer memory unit

Info

Publication number
JPS5562579A
JPS5562579A JP13386678A JP13386678A JPS5562579A JP S5562579 A JPS5562579 A JP S5562579A JP 13386678 A JP13386678 A JP 13386678A JP 13386678 A JP13386678 A JP 13386678A JP S5562579 A JPS5562579 A JP S5562579A
Authority
JP
Japan
Prior art keywords
data
unit
buffer memory
cpu1
detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13386678A
Other languages
Japanese (ja)
Inventor
Takashi Sakai
Isao Aizawa
Noriyuki Toyoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13386678A priority Critical patent/JPS5562579A/en
Publication of JPS5562579A publication Critical patent/JPS5562579A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to process simply errors generated in a part other than desired data, by providing error detectors between a main memory and a buffer memory and between the buffer memory and a CPU respectively.
CONSTITUTION: When data requested by CPU1 does not exist in buffer memory unit 3, a data block is transferred from unit 2 to unit 3. At this time, agreement between data including requested data and check bits is checked by error detector 4; if correct data is not obtained, it is reported to CPU1. Continuously, data other than desired data and check bits are sent from unit 2, and the check result dependent upon detector 4 is stored in unit 3 together with parity bits P0 and P1 generated from parity bit generators 5 and 6. Next, when data requested by CPU1 exists, data in unit 3 is read out and is checked by error detector 7. Detector 7 checks data with parity bits P0 and P1; and if an error is detected, it is reported to CPU1.
COPYRIGHT: (C)1980,JPO&Japio
JP13386678A 1978-10-31 1978-10-31 Control system of buffer memory unit Pending JPS5562579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13386678A JPS5562579A (en) 1978-10-31 1978-10-31 Control system of buffer memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13386678A JPS5562579A (en) 1978-10-31 1978-10-31 Control system of buffer memory unit

Publications (1)

Publication Number Publication Date
JPS5562579A true JPS5562579A (en) 1980-05-12

Family

ID=15114875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13386678A Pending JPS5562579A (en) 1978-10-31 1978-10-31 Control system of buffer memory unit

Country Status (1)

Country Link
JP (1) JPS5562579A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63226751A (en) * 1987-03-17 1988-09-21 Nec Corp Bus error control system for cache memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63226751A (en) * 1987-03-17 1988-09-21 Nec Corp Bus error control system for cache memory

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