JPS5543608A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5543608A
JPS5543608A JP11508678A JP11508678A JPS5543608A JP S5543608 A JPS5543608 A JP S5543608A JP 11508678 A JP11508678 A JP 11508678A JP 11508678 A JP11508678 A JP 11508678A JP S5543608 A JPS5543608 A JP S5543608A
Authority
JP
Japan
Prior art keywords
bit
data
parity
bit width
bus line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11508678A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Kazuyuki Sato
Keikichi Tamaru
Tai Sato
Isamu Yamazaki
Misao Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11508678A priority Critical patent/JPS5543608A/en
Publication of JPS5543608A publication Critical patent/JPS5543608A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To ensure a quick check for the error bit by dividing the bit width of the data and then giving the parity to each divided bit width.
CONSTITUTION: The data featuring the 32-bit width on the data bus line and given from the main memory device is converted into the data of 16-bit width through information converter 500 and then sent out to the bus line to the CPU. Parity bit generators 901W904 generates one bit of parity with every 8 bits of the 32-bit width data and then sends it out onto the data bus line via NAND's 905W908. At the same time, the exclusive logic sum is obtained through gates 909W912 between the parity bit added to the information read out from the main memory device and the parity generated from generators 901W904, and thus the error is detected.
COPYRIGHT: (C)1980,JPO&Japio
JP11508678A 1978-09-21 1978-09-21 Electronic computer Pending JPS5543608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11508678A JPS5543608A (en) 1978-09-21 1978-09-21 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11508678A JPS5543608A (en) 1978-09-21 1978-09-21 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5543608A true JPS5543608A (en) 1980-03-27

Family

ID=14653840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11508678A Pending JPS5543608A (en) 1978-09-21 1978-09-21 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5543608A (en)

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