JPS5543607A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5543607A
JPS5543607A JP11508578A JP11508578A JPS5543607A JP S5543607 A JPS5543607 A JP S5543607A JP 11508578 A JP11508578 A JP 11508578A JP 11508578 A JP11508578 A JP 11508578A JP S5543607 A JPS5543607 A JP S5543607A
Authority
JP
Japan
Prior art keywords
bit width
cpu
converter
bit
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11508578A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Kazuyuki Sato
Keikichi Tamaru
Tai Sato
Isamu Yamazaki
Misao Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11508578A priority Critical patent/JPS5543607A/en
Publication of JPS5543607A publication Critical patent/JPS5543607A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To reduce the number of the package pins and then to realize the data conversion through the different bit widths by installing the converter of the bit width between the CPU and the main memory device. CONSTITUTION:The bus line of 16-bit width sent from the CPU is converted into the line of 32-bit width through information converter 500 and then connected to main memory device 100. The information of 32-bit width read out of device 100 at the 1st step is registered into plural 8-bit registers within converter 500 to be then taken into the CPU with the 16-bit width. In this way, the memory access apeed is increased, at the same time decreasing the number of the connection lines between the CPU and the outside.
JP11508578A 1978-09-21 1978-09-21 Electronic computer Pending JPS5543607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11508578A JPS5543607A (en) 1978-09-21 1978-09-21 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11508578A JPS5543607A (en) 1978-09-21 1978-09-21 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5543607A true JPS5543607A (en) 1980-03-27

Family

ID=14653812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11508578A Pending JPS5543607A (en) 1978-09-21 1978-09-21 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5543607A (en)

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