JPS5543604A - Electronic computer - Google Patents

Electronic computer

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Publication number
JPS5543604A
JPS5543604A JP11508278A JP11508278A JPS5543604A JP S5543604 A JPS5543604 A JP S5543604A JP 11508278 A JP11508278 A JP 11508278A JP 11508278 A JP11508278 A JP 11508278A JP S5543604 A JPS5543604 A JP S5543604A
Authority
JP
Japan
Prior art keywords
register
registered
address
common bus
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11508278A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Kazuyuki Sato
Keikichi Tamaru
Tai Sato
Isamu Yamazaki
Misao Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11508278A priority Critical patent/JPS5543604A/en
Publication of JPS5543604A publication Critical patent/JPS5543604A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To realize a compact-design and high operation speed CPU by performing the LSI formation for the CPU and the advanced taking of the order.
CONSTITUTION: The information read out from main memory device 100 is registered into instruction register 202, and the OP part of register 202 is decoded by decoder 203 to decide which address of ROM205 the sequence starts from. This decoded address is registered in ROM address register 204. Based on the address signals sent from register 204, the data is read out from ROM205 to be then registered into microinstruction register 209. The data, if its bit length is larger than the common bus, is divided to be registered into the register. The common bus features 16 bits to perform the transfer between the CPU and the I/O, and the data length longer than the common bus will do.
COPYRIGHT: (C)1980,JPO&Japio
JP11508278A 1978-09-21 1978-09-21 Electronic computer Pending JPS5543604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11508278A JPS5543604A (en) 1978-09-21 1978-09-21 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11508278A JPS5543604A (en) 1978-09-21 1978-09-21 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5543604A true JPS5543604A (en) 1980-03-27

Family

ID=14653732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11508278A Pending JPS5543604A (en) 1978-09-21 1978-09-21 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5543604A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175146A (en) * 1984-02-20 1985-09-09 Hitachi Ltd Programmable controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175146A (en) * 1984-02-20 1985-09-09 Hitachi Ltd Programmable controller
JPH0317135B2 (en) * 1984-02-20 1991-03-07 Hitachi Ltd

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