JPS5533278A - Error correcting processor - Google Patents

Error correcting processor

Info

Publication number
JPS5533278A
JPS5533278A JP10649078A JP10649078A JPS5533278A JP S5533278 A JPS5533278 A JP S5533278A JP 10649078 A JP10649078 A JP 10649078A JP 10649078 A JP10649078 A JP 10649078A JP S5533278 A JPS5533278 A JP S5533278A
Authority
JP
Japan
Prior art keywords
error
data
byte
check
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10649078A
Other languages
Japanese (ja)
Inventor
Osamu Araya
Yutaka Kamiyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10649078A priority Critical patent/JPS5533278A/en
Publication of JPS5533278A publication Critical patent/JPS5533278A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To make error corrections without interrupting a process if a two-bit error does not exceeds one byte, by correcting a multi-bit error by a one-byte block corrector.
CONSTITUTION: Data from CPU are set to write data register WDR and also written into memory unit MSU, and check byte generator CG generates check bytes C1 and C2, which are written into memory unit MSU. In read operation, multiplexer MPX inputs the data to error detector ED equipped with the syndrome generator and error decision unit and if an error detected, it is corrected by data regenerator EC. Further, its result is passed through multiplexer MPX and error detector ED to makes a check on that data regenerator EC is operating accurately, thereby sending data out to CPU via read data register RDR.
COPYRIGHT: (C)1980,JPO&Japio
JP10649078A 1978-08-31 1978-08-31 Error correcting processor Pending JPS5533278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10649078A JPS5533278A (en) 1978-08-31 1978-08-31 Error correcting processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10649078A JPS5533278A (en) 1978-08-31 1978-08-31 Error correcting processor

Publications (1)

Publication Number Publication Date
JPS5533278A true JPS5533278A (en) 1980-03-08

Family

ID=14434892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10649078A Pending JPS5533278A (en) 1978-08-31 1978-08-31 Error correcting processor

Country Status (1)

Country Link
JP (1) JPS5533278A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741052A (en) * 1980-08-26 1982-03-06 Nec Corp Burst error correcting system applied to recording device or transmission device of series data byte
JPS57157654A (en) * 1981-03-25 1982-09-29 Mitsubishi Electric Corp Error correcting circuit
JPS6250943A (en) * 1985-08-30 1987-03-05 Hitachi Ltd Memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741052A (en) * 1980-08-26 1982-03-06 Nec Corp Burst error correcting system applied to recording device or transmission device of series data byte
JPS57157654A (en) * 1981-03-25 1982-09-29 Mitsubishi Electric Corp Error correcting circuit
JPS6250943A (en) * 1985-08-30 1987-03-05 Hitachi Ltd Memory device

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