JPS5523518A - Adder circuit having error check and correction function - Google Patents

Adder circuit having error check and correction function

Info

Publication number
JPS5523518A
JPS5523518A JP9420778A JP9420778A JPS5523518A JP S5523518 A JPS5523518 A JP S5523518A JP 9420778 A JP9420778 A JP 9420778A JP 9420778 A JP9420778 A JP 9420778A JP S5523518 A JPS5523518 A JP S5523518A
Authority
JP
Japan
Prior art keywords
parity
carry
errors
sum
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9420778A
Other languages
Japanese (ja)
Other versions
JPS576617B2 (en
Inventor
Eiji Fujiwara
Kazuo Haruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9420778A priority Critical patent/JPS5523518A/en
Publication of JPS5523518A publication Critical patent/JPS5523518A/en
Publication of JPS576617B2 publication Critical patent/JPS576617B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To make it possible to correct errors in a block and applying this system to a bit slice type easily by using the horizontal and vertical parity check system where parity codes are orthogonal to each other and doubling carry generation to check errors.
CONSTITUTION: Parity codes for data A and B the parity result for addition results SO to Sn-1 are denoted as PA, PB and PS respectively, and they are inputted full- sum parity comparator 9 where output PS of parity I calculator 7 and output P'S= (PA⊕PB⊕PC, however, PC is a parity code dependent upon carry resultc C) of parity I forecasting equipment 5 are compared with each other, thereby outputting error block indication signal ES (=PS⊕P'S). Here, errors are detected in case of ES=1. When a bit slica-type adder-carry dependent sum adder is used specially, all carry errors and all odd bit error in the addition result can be detected in case of the execution of full-sum parity check. Then, carry error result EC is outputted by comparing double carry and carry with each other in comparator 13.
COPYRIGHT: (C)1980,JPO&Japio
JP9420778A 1978-08-02 1978-08-02 Adder circuit having error check and correction function Granted JPS5523518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9420778A JPS5523518A (en) 1978-08-02 1978-08-02 Adder circuit having error check and correction function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9420778A JPS5523518A (en) 1978-08-02 1978-08-02 Adder circuit having error check and correction function

Publications (2)

Publication Number Publication Date
JPS5523518A true JPS5523518A (en) 1980-02-20
JPS576617B2 JPS576617B2 (en) 1982-02-05

Family

ID=14103852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9420778A Granted JPS5523518A (en) 1978-08-02 1978-08-02 Adder circuit having error check and correction function

Country Status (1)

Country Link
JP (1) JPS5523518A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116853A (en) * 1982-12-20 1984-07-05 スペリ・コ−ポレ−シヨン Apparatus for creating multiplication pipeline of arbitrary size

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193307U (en) * 1984-11-26 1986-06-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116853A (en) * 1982-12-20 1984-07-05 スペリ・コ−ポレ−シヨン Apparatus for creating multiplication pipeline of arbitrary size

Also Published As

Publication number Publication date
JPS576617B2 (en) 1982-02-05

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