JPS5523518A - Adder circuit having error check and correction function - Google Patents
Adder circuit having error check and correction functionInfo
- Publication number
- JPS5523518A JPS5523518A JP9420778A JP9420778A JPS5523518A JP S5523518 A JPS5523518 A JP S5523518A JP 9420778 A JP9420778 A JP 9420778A JP 9420778 A JP9420778 A JP 9420778A JP S5523518 A JPS5523518 A JP S5523518A
- Authority
- JP
- Japan
- Prior art keywords
- parity
- carry
- errors
- sum
- result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE: To make it possible to correct errors in a block and applying this system to a bit slice type easily by using the horizontal and vertical parity check system where parity codes are orthogonal to each other and doubling carry generation to check errors.
CONSTITUTION: Parity codes for data A and B the parity result for addition results SO to Sn-1 are denoted as PA, PB and PS respectively, and they are inputted full- sum parity comparator 9 where output PS of parity I calculator 7 and output P'S= (PA⊕PB⊕PC, however, PC is a parity code dependent upon carry resultc C) of parity I forecasting equipment 5 are compared with each other, thereby outputting error block indication signal ES (=PS⊕P'S). Here, errors are detected in case of ES=1. When a bit slica-type adder-carry dependent sum adder is used specially, all carry errors and all odd bit error in the addition result can be detected in case of the execution of full-sum parity check. Then, carry error result EC is outputted by comparing double carry and carry with each other in comparator 13.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9420778A JPS5523518A (en) | 1978-08-02 | 1978-08-02 | Adder circuit having error check and correction function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9420778A JPS5523518A (en) | 1978-08-02 | 1978-08-02 | Adder circuit having error check and correction function |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5523518A true JPS5523518A (en) | 1980-02-20 |
JPS576617B2 JPS576617B2 (en) | 1982-02-05 |
Family
ID=14103852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9420778A Granted JPS5523518A (en) | 1978-08-02 | 1978-08-02 | Adder circuit having error check and correction function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5523518A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59116853A (en) * | 1982-12-20 | 1984-07-05 | スペリ・コ−ポレ−シヨン | Apparatus for creating multiplication pipeline of arbitrary size |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6193307U (en) * | 1984-11-26 | 1986-06-17 |
-
1978
- 1978-08-02 JP JP9420778A patent/JPS5523518A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59116853A (en) * | 1982-12-20 | 1984-07-05 | スペリ・コ−ポレ−シヨン | Apparatus for creating multiplication pipeline of arbitrary size |
Also Published As
Publication number | Publication date |
---|---|
JPS576617B2 (en) | 1982-02-05 |
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