JPS57147732A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS57147732A
JPS57147732A JP56033689A JP3368981A JPS57147732A JP S57147732 A JPS57147732 A JP S57147732A JP 56033689 A JP56033689 A JP 56033689A JP 3368981 A JP3368981 A JP 3368981A JP S57147732 A JPS57147732 A JP S57147732A
Authority
JP
Japan
Prior art keywords
transmission
reception
code
circuit
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56033689A
Other languages
Japanese (ja)
Inventor
Hirotaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56033689A priority Critical patent/JPS57147732A/en
Publication of JPS57147732A publication Critical patent/JPS57147732A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

PURPOSE:To improve the reliability by detecting code errors, by using a transfer line to transfer the check bit between a main memory controller and a input and output controller to transmit an abnormal signal when abnormality is occured. CONSTITUTION:In a parity transmission/reception controlling circuit A11, a parity check bit against the transferred data from a data transmission/reception controllig circuit 1 is produced, and this is transferred to a parity transmission/ reception controlling circuit B13 in a main memory controller 9. In the parity transmission/reception controlling circuit B13, the data from a data transmission/reception controlling circuit 3 and the parity check bit from the parity transmission/reception controlling circuit A11 are received to perform the parity check. The result is treansferred to a code transmission/reception circuit 7 for correction. A code which detects errors impossible to be corrected is produced against the data sent from the data transmission/reception circuit 3 by a code transmission/reception circuit for correction 7. This code is stored in a main memory device 10 in the same manner as the code for correction.
JP56033689A 1981-03-09 1981-03-09 Data transfer controller Pending JPS57147732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56033689A JPS57147732A (en) 1981-03-09 1981-03-09 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56033689A JPS57147732A (en) 1981-03-09 1981-03-09 Data transfer controller

Publications (1)

Publication Number Publication Date
JPS57147732A true JPS57147732A (en) 1982-09-11

Family

ID=12393389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56033689A Pending JPS57147732A (en) 1981-03-09 1981-03-09 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS57147732A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03291787A (en) * 1990-04-10 1991-12-20 Matsushita Electric Ind Co Ltd Memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03291787A (en) * 1990-04-10 1991-12-20 Matsushita Electric Ind Co Ltd Memory device

Similar Documents

Publication Publication Date Title
GB2282244B (en) Integrated circuit
JPS57147732A (en) Data transfer controller
JPS5452908A (en) Data transfer device
JPS5452907A (en) Data transfer unit
JPS5694597A (en) Memory data control system
JPS6465955A (en) Communication system
JPS5797250A (en) Data transmission system for automatic retransmission request system
JPS5627456A (en) Read data transfer system
JPS56162078A (en) Electronic clock
JPS57160241A (en) Error controller
JPS5542318A (en) Cash memory control system
JPS55130255A (en) Transmission control system
JPS57207959A (en) Parity producing system of erroneous bit correcting device
JPS577647A (en) Fault processing system
JPS56166655A (en) Data relief system
JPS57160240A (en) Error controller
JPS6439851A (en) Distribution control type exchanging device
JPS54108504A (en) Data transmission system on start-stop system
JPS56129952A (en) Error correction system
JPS5762645A (en) Information transfer system
JPS55150634A (en) Transmission error detecting system of communication control unit
JPS52130244A (en) Memory unit providing error control function
JPS56153592A (en) Output memory device
JPS57202150A (en) Reception information checking method
JPS56149651A (en) Checking system of parity detecting function