JPS5694597A - Memory data control system - Google Patents
Memory data control systemInfo
- Publication number
- JPS5694597A JPS5694597A JP17319079A JP17319079A JPS5694597A JP S5694597 A JPS5694597 A JP S5694597A JP 17319079 A JP17319079 A JP 17319079A JP 17319079 A JP17319079 A JP 17319079A JP S5694597 A JPS5694597 A JP S5694597A
- Authority
- JP
- Japan
- Prior art keywords
- sec
- ded
- data
- parity
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To enable to use the data corrected with SEC-DED system, if there is an error, by controlling the selective output means for the output of SEC-DED means and the data output according to the result of parity inspection.
CONSTITUTION: The data memory 3 storing the data including the parity bit. parity inspection circuit 9, and 1-bit error correction - 2-bit error detection (SEC- DED) means 1, are provided. Further, the output from the SEC-DED means 1 and the data read out from the data memory section 3 are delivered, and the selective output means selectively outputting either one of them, is provided, and this selective output means is controlled according to the result of inspection in the parity inspection circuit 9. For example, as the selective output means, a multiplexer 6 is used, and normally, check is made with the parity system, and if there is any error, the data corrected with the SEC-DED system can be output.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17319079A JPS5694597A (en) | 1979-12-28 | 1979-12-28 | Memory data control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17319079A JPS5694597A (en) | 1979-12-28 | 1979-12-28 | Memory data control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5694597A true JPS5694597A (en) | 1981-07-31 |
Family
ID=15955755
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17319079A Pending JPS5694597A (en) | 1979-12-28 | 1979-12-28 | Memory data control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5694597A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6151253A (en) * | 1984-08-20 | 1986-03-13 | Nec Corp | Memory error correctng circuit |
JPS62125453A (en) * | 1985-11-26 | 1987-06-06 | Iwaki Denshi Kk | Storage device |
JPS63240658A (en) * | 1987-03-27 | 1988-10-06 | Nec Corp | Memory device |
JP2016187099A (en) * | 2015-03-27 | 2016-10-27 | ルネサスエレクトロニクス株式会社 | Data processing circuit |
US10859417B2 (en) | 2016-03-11 | 2020-12-08 | Hitachi Metals, Ltd. | Thermal mass flow sensor, method for manufacturing the thermal mass flow sensor, and thermal mass flow meter using the thermal mass flow sensor |
-
1979
- 1979-12-28 JP JP17319079A patent/JPS5694597A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6151253A (en) * | 1984-08-20 | 1986-03-13 | Nec Corp | Memory error correctng circuit |
JPS62125453A (en) * | 1985-11-26 | 1987-06-06 | Iwaki Denshi Kk | Storage device |
JPS63240658A (en) * | 1987-03-27 | 1988-10-06 | Nec Corp | Memory device |
JP2016187099A (en) * | 2015-03-27 | 2016-10-27 | ルネサスエレクトロニクス株式会社 | Data processing circuit |
US10340955B2 (en) | 2015-03-27 | 2019-07-02 | Renesas Electronics Corporation | Data processing circuit |
US10859417B2 (en) | 2016-03-11 | 2020-12-08 | Hitachi Metals, Ltd. | Thermal mass flow sensor, method for manufacturing the thermal mass flow sensor, and thermal mass flow meter using the thermal mass flow sensor |
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