JPS56163596A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS56163596A
JPS56163596A JP6483580A JP6483580A JPS56163596A JP S56163596 A JPS56163596 A JP S56163596A JP 6483580 A JP6483580 A JP 6483580A JP 6483580 A JP6483580 A JP 6483580A JP S56163596 A JPS56163596 A JP S56163596A
Authority
JP
Japan
Prior art keywords
gate
error
signal
byte position
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6483580A
Other languages
Japanese (ja)
Inventor
Koji Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6483580A priority Critical patent/JPS56163596A/en
Publication of JPS56163596A publication Critical patent/JPS56163596A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To obtain a normal data even though an error exists in both words of a doubled memory, by dividing each word within two memories into plural subgroups and then giving a check to the data with every subgroup. CONSTITUTION:No error exists at the byte position i (i=0-3) of a temporary register 3, and an error exists at the byte position i of a register 3'. In such case, a gate Gi opens by the data effective signal Si sent from a parity check circuit PCi, and a gate G'i is closed since the signal S'i of a parity check circuit PC'i is off. As a result, the output of Gi, i.e., a normal data is set at the byte position i of a reading register 5. In this case, the error detection signal ei of the circuit PCi is off. Thus an AND gate Gei is closed to deliver no error signal E to the system. The system has no breakdown as long as the position of the faulty subgroup differs and even though a fault exists in both doubled memories.
JP6483580A 1980-05-16 1980-05-16 Memory control system Pending JPS56163596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6483580A JPS56163596A (en) 1980-05-16 1980-05-16 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6483580A JPS56163596A (en) 1980-05-16 1980-05-16 Memory control system

Publications (1)

Publication Number Publication Date
JPS56163596A true JPS56163596A (en) 1981-12-16

Family

ID=13269695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6483580A Pending JPS56163596A (en) 1980-05-16 1980-05-16 Memory control system

Country Status (1)

Country Link
JP (1) JPS56163596A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134619A (en) * 1990-04-06 1992-07-28 Sf2 Corporation Failure-tolerant mass storage system
US5140592A (en) * 1990-03-02 1992-08-18 Sf2 Corporation Disk array system
US5146574A (en) * 1989-06-27 1992-09-08 Sf2 Corporation Method and circuit for programmable selecting a variable sequence of element using write-back
US5202856A (en) * 1990-04-05 1993-04-13 Micro Technology, Inc. Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports
US5212785A (en) * 1990-04-06 1993-05-18 Micro Technology, Inc. Apparatus and method for controlling data flow between a computer and memory devices
US5214778A (en) * 1990-04-06 1993-05-25 Micro Technology, Inc. Resource management in a multiple resource system
US5233692A (en) * 1990-04-06 1993-08-03 Micro Technology, Inc. Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
US5315708A (en) * 1990-02-28 1994-05-24 Micro Technology, Inc. Method and apparatus for transferring data through a staging memory
US5325497A (en) * 1990-03-29 1994-06-28 Micro Technology, Inc. Method and apparatus for assigning signatures to identify members of a set of mass of storage devices
US5388243A (en) * 1990-03-09 1995-02-07 Mti Technology Corporation Multi-sort mass storage device announcing its active paths without deactivating its ports in a network architecture
US5414818A (en) * 1990-04-06 1995-05-09 Mti Technology Corporation Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol
US5461723A (en) * 1990-04-05 1995-10-24 Mit Technology Corp. Dual channel data block transfer bus
US5469453A (en) * 1990-03-02 1995-11-21 Mti Technology Corporation Data corrections applicable to redundant arrays of independent disks
US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349686A (en) * 1989-06-27 1994-09-20 Mti Technology Corporation Method and circuit for programmably selecting a variable sequence of elements using write-back
US5146574A (en) * 1989-06-27 1992-09-08 Sf2 Corporation Method and circuit for programmable selecting a variable sequence of element using write-back
US5315708A (en) * 1990-02-28 1994-05-24 Micro Technology, Inc. Method and apparatus for transferring data through a staging memory
US5140592A (en) * 1990-03-02 1992-08-18 Sf2 Corporation Disk array system
US5469453A (en) * 1990-03-02 1995-11-21 Mti Technology Corporation Data corrections applicable to redundant arrays of independent disks
US5388243A (en) * 1990-03-09 1995-02-07 Mti Technology Corporation Multi-sort mass storage device announcing its active paths without deactivating its ports in a network architecture
US5325497A (en) * 1990-03-29 1994-06-28 Micro Technology, Inc. Method and apparatus for assigning signatures to identify members of a set of mass of storage devices
US5202856A (en) * 1990-04-05 1993-04-13 Micro Technology, Inc. Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports
US5461723A (en) * 1990-04-05 1995-10-24 Mit Technology Corp. Dual channel data block transfer bus
US5212785A (en) * 1990-04-06 1993-05-18 Micro Technology, Inc. Apparatus and method for controlling data flow between a computer and memory devices
US5361347A (en) * 1990-04-06 1994-11-01 Mti Technology Corporation Resource management in a multiple resource system where each resource includes an availability state stored in a memory of the resource
US5233692A (en) * 1990-04-06 1993-08-03 Micro Technology, Inc. Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
US5414818A (en) * 1990-04-06 1995-05-09 Mti Technology Corporation Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol
US5454085A (en) * 1990-04-06 1995-09-26 Mti Technology Corporation Method and apparatus for an enhanced computer system interface
US5214778A (en) * 1990-04-06 1993-05-25 Micro Technology, Inc. Resource management in a multiple resource system
US5134619A (en) * 1990-04-06 1992-07-28 Sf2 Corporation Failure-tolerant mass storage system
US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources

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