GB1486362A - Interface module for a digital data transmission system - Google Patents

Interface module for a digital data transmission system

Info

Publication number
GB1486362A
GB1486362A GB1216575A GB1216575A GB1486362A GB 1486362 A GB1486362 A GB 1486362A GB 1216575 A GB1216575 A GB 1216575A GB 1216575 A GB1216575 A GB 1216575A GB 1486362 A GB1486362 A GB 1486362A
Authority
GB
United Kingdom
Prior art keywords
module
register
words
word
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1216575A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Singer Co
Original Assignee
Singer Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Singer Co filed Critical Singer Co
Priority to GB1216575A priority Critical patent/GB1486362A/en
Publication of GB1486362A publication Critical patent/GB1486362A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Selective Calling Equipment (AREA)
  • Communication Control (AREA)

Abstract

1486362 Digital data transmission SINGER CO 24 March 1975 12165/75 Heading H4P [Also in Division G4] An interface module 10 is provided for coupling a subsystem, e.g. a computer, a remote terminal, a sensor or an output device of a digital data transmission system to a data link P, the module being operable in either a "receive" or a "transmit" mode; in the "receive" mode multisection control words and data words are decoded 108, 110, 112 and the different sections of the control words are directed by means of logic circuitry to different ones of a set of logic elements 120, 122, 124 and 126 coupled in parallel to a common bus 114 leading from the decoder. Each control word has the format illustrated in Fig. 3 (not shown), and includes an address portion which is used to select the required subsystem by means of a comparator 150 coupled to the address register 120, and a word count portion which is used in conjunction with a word counter 152 coupled to the word count register 122 to indicate how many data words are to be expected following a control word. A single bit of each control word is fed to register 124 to set the module in either the "receive" or the "transmit" mode. The entire control word is stored in register 126, and the data words are stored in an I/O register 128. Further registers 130, 132 are provided for conventional checking and testing purposes, and a parity checking circuit 116 is also provided. The logic circuitry for dividing the control words into their various sections includes a read-only memory 134 controlled by timing signals from a timebase generator 176 and a counter 178. When the module 10 is set to its "transmit" mode, data words from I/O register 128 and portions of control words from the logic elements 120, 122, 124 and 126 are fed via a common bus 156 to be encoded 160, 162 and 164 and then sent via a pulse shaper 170 and amplifiers 172, 174 to the data link P for transmission. A plurality of interface modules such as 10 are coupled in parallel (Fig. 1, not shown) so that, in the event of failure of a logic element of a module, a suitable logic element of another module may be substituted therefor by means of selector circuits such as 10a, 10b. Each interface module is constructed using three integrated circuit chips 100, 102 and 104.
GB1216575A 1975-03-24 1975-03-24 Interface module for a digital data transmission system Expired GB1486362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1216575A GB1486362A (en) 1975-03-24 1975-03-24 Interface module for a digital data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1216575A GB1486362A (en) 1975-03-24 1975-03-24 Interface module for a digital data transmission system

Publications (1)

Publication Number Publication Date
GB1486362A true GB1486362A (en) 1977-09-21

Family

ID=9999546

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1216575A Expired GB1486362A (en) 1975-03-24 1975-03-24 Interface module for a digital data transmission system

Country Status (1)

Country Link
GB (1) GB1486362A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005045A1 (en) * 1978-04-20 1979-10-31 Network Systems Corporation Data-pulse communication system and adapter
EP0081238A2 (en) * 1981-12-09 1983-06-15 Hitachi, Ltd. Multi-computer system
US4485439A (en) * 1982-07-27 1984-11-27 S.A. Analis Standard hardware-software interface for connecting any instrument which provides a digital output stream with any digital host computer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005045A1 (en) * 1978-04-20 1979-10-31 Network Systems Corporation Data-pulse communication system and adapter
EP0081238A2 (en) * 1981-12-09 1983-06-15 Hitachi, Ltd. Multi-computer system
EP0081238A3 (en) * 1981-12-09 1985-11-27 Hitachi, Ltd. Multi-computer system
US4485439A (en) * 1982-07-27 1984-11-27 S.A. Analis Standard hardware-software interface for connecting any instrument which provides a digital output stream with any digital host computer

Similar Documents

Publication Publication Date Title
EP0362050A3 (en) Memory card
EP0377455A3 (en) Test mode switching system for lsi
GB1486362A (en) Interface module for a digital data transmission system
GB1475720A (en) Junction units
GB1391976A (en) Information stores
JPS5694596A (en) Memory control system
JPS6321932B2 (en)
JPS5835284B2 (en) Data bus check method
JPS6478497A (en) Semiconductor memory
JPS5727342A (en) Error checking system for error detecting correcting circuit
JPS5782298A (en) Diagnostic system for storage device
SU1312591A1 (en) Interface for linking electronic computer with peripheral unit
SU1151977A1 (en) Information input device
JPS5539935A (en) Paper tape reading device
SU1175777A1 (en) Device for telecontrolling engineering entities of underground railway
RU2047918C1 (en) Device for programming read-only memory chips
SU1571786A1 (en) Test text transmitter
RU1805496C (en) Memory circuit
GB1018762A (en) Data transfer system
JPS57162194A (en) Writing device in read-only memory (rom)
JPS6086607A (en) Sequence control system of data process
JPS57202149A (en) Information transmitting system
GB1446995A (en) Device for detecint the occurrence of identical binary words during a same cycle
JPS5621264A (en) Multiplex external memory unit
JPS57162550A (en) Battery checking system

Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930324