JPS6086607A - Sequence control system of data process - Google Patents

Abstract

PURPOSE:To make a complicated control possible with a simple constitution by providing a register for sequence control and a register for address input in the output side of an ROM and operating both registers alternately with clock pulses and giving the output of one register as a switching signal of the ROM. CONSTITUTION:Two registers RG1 and RG2 are connected to the output side of the ROM in a sequence control system, and these registers RG1 and RG2 are operated alternately by a switching signal OSS outputted through a logic circuit ROC to store the output of the ROM. The output of the register RG2 is fed back as an address of the ROM, and a required code is generated by combination between status data SD and input data ID and is stored in the register RG2. Thus, a complicated control is possible with a simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for controlling the order of data processes in various electronic circuit systems.

Background of technology In various electronic circuit systems, such as electronic switching systems, electronic computer systems, and electronic control systems for various devices, data processing progresses in order for each system to perform its intended function. It is necessary to control the order correctly.

For example, in the facsimile transmission system shown in Figure 1 as Block Daito Dalam, the input side terminal device L is activated and the information on the inserted original paper 2 is transmitted via the terminal station 3 to the line 4.
Until the transmission is completed, status data and signals are sent and received as the data process progresses as described below.

(1) A star 11 meter is sent from the terminal device 1 to the terminal station 3, and the terminal station enters the preparation state.

(2) Once a synchronization signal is sent from the terminal device 1 and the terminal station 3 enters a synchronized state, its status data is sent to the terminal device l.

(3) In response to the status data, information on the inserted original paper 2 is sent from the terminal device 1.

(4) Once the information transmission of the original paper 2 is completed, the status data is received and an end signal is transmitted L3.

Receiver (1) Terminal 5 for transmitting and receiving the above status data and signals
, and the receiving terminal device 6, status data and signals are sent and received according to the order of progress of the process.

In this way, in a process control system, correct process control is performed only after receiving state data indicating each state according to the order of progress of the processes, and then sending the corresponding signal to the next process. .

For this purpose, for example, a read-on-memory IJ is installed in the terminal station 3.5 to control the required process order 11i1J.
A control circuit using ROM is provided.

(C) Prior art f Problems Figure 2 shows the lead/lead type conventionally used for the above purpose.
This block diagram shows an example of a control circuit using an on-memory ROM, in which the output of the read-on memory ROM is latched by a register RG controlled by a clock pulse CLK, and the data is read and output. It is used as address inputs A and D of the on-memory ROM, and the next state is determined by the combination of the previous state data and input data ID, and the data SD indicating the constant state of q♂ is sent to the decoder DEC. and control signal C
It is designed to be used as 3.

In such a conventional circuit configuration, a decoder DEC that detects a specific data is required to obtain the necessary control signals, and it is also difficult to obtain control signals for multiple hits at once, making it difficult to obtain read/write signals.
The number of data that does not return to the address as the output state data SD of the on-memory ROM becomes the control tn signal CS is reduced, and complicated control becomes impossible.

With the increase in the capacity of read-on memory ROMs, the number of manual address bits is on the rise, but the number of output data bits is usually I-Hide (8 bits), and is for special purposes. Generally lead-on memo 1 except
Month? ○Even if the capacity of M increases, it will not increase.

Therefore, in the conventional circuit configuration, the number of hits required by human power is 8 bits at most, and there is a limit to the control content that can only be obtained with 256 (2Q) 8th power) state data.

fd1 OBJECTS OF THE INVENTION It is an object of the present invention to provide a new scheme which eliminates the above-mentioned drawbacks of conventional circuit arrangements used for sequential control of data processes.

te1 Structure of the Invention The above object is to control the order of data processing by using a read-on memory and adding its output data to the address input of the memory. and a register for a sequence control function, the two registers being operated alternately by a clock pulse, and the pulse being applied to the input side of the memory as an output switching signal. This is achieved by the order control method of the present invention, which is configured to do so.

That is, in the present invention, an output switching signal is provided to a part of the address inputs of the read-on memory, which is increasing due to the increase in capacity, and by switching the output using the signal, a multi-bit output is obtained. In addition to increasing the number of states and improving the control content, the read-on memory itself can have a decoder function to directly obtain data necessary for control.

(F1 Embodiment of the Invention) The gist of the present invention will be specifically explained below with reference to the embodiment shown in FIG.

The read-on memo is not divided into one for the control signal cs and one for the status data SD as in the past, but both have two registers RGI.
, is guided by RG2. The two registers RGI
, RG2 are alternately activated by clock pulses CLJ<Nyo~ζ, which are applied alternately to each other depending on the polarity of the output switching signal oss via the logic circuit ROCli, and are synchronously activated by human power +J1. l+6;
The output of JRO'M is sent to register HGI or RG2.
The output of the L disk 11G2 is fed back as an address of the read-on memory ROM. Further, in the register RG2, necessary codes are created and stored in the read-men memory ROM based on the combination of status data and input data.

(As described in the detailed description of the invention, in the method of the present invention, the output of the read-on memory used can be alternately fully used for control signals or status data.
It enables complex control with a simple configuration, and its industrial effects are remarkable.

[Brief explanation of drawings]

Figure 1 shows a block diagram of the configuration of a facsimile transmission system as an example that requires a data process order control system, and Figure 2 shows a conventional system for order control using an F-on-memory ROM. An example of the method is shown in a block diagram, and FIG.
The embodiment is also shown in a block diagram. In the figure, ROM is read-on memory, RG, R
GI and RG2 are registers, ID is input data, SD
is status data, 80 is address input, CS is control signal,
DEC is a decoder, ROC is a logic circuit, OSS is an output switching signal, CL, K is 1 fig. 2 flash 47) Mine 3 fig. θC

Claims (1)

[Claims] In a system that uses a read-on memory and adds its output data to the address input of the memory to control the order of the CC deck process, a register for address input and a register for order control are provided on the output side of the memory. registers are provided for 51. and the two registers are set to 51. 1. A method for controlling the sequence of data processes in various electronic circuit systems, characterized in that the pulses are operated alternately and the pulses are applied to the input side of the memory as an output switching signal.