JPH0531183B2 - - Google Patents

Info

Publication number
JPH0531183B2
JPH0531183B2 JP58003040A JP304083A JPH0531183B2 JP H0531183 B2 JPH0531183 B2 JP H0531183B2 JP 58003040 A JP58003040 A JP 58003040A JP 304083 A JP304083 A JP 304083A JP H0531183 B2 JPH0531183 B2 JP H0531183B2
Authority
JP
Japan
Prior art keywords
data
cpu
optional
cpus
host cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58003040A
Other languages
Japanese (ja)
Other versions
JPS59127133A (en
Inventor
Masazumi Ito
Kenji Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Minolta Co Ltd
Original Assignee
Minolta Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minolta Co Ltd filed Critical Minolta Co Ltd
Priority to JP58003040A priority Critical patent/JPS59127133A/en
Priority to FR8400216A priority patent/FR2539260B1/en
Priority to DE19843400464 priority patent/DE3400464A1/en
Publication of JPS59127133A publication Critical patent/JPS59127133A/en
Priority to US07/062,562 priority patent/US4847756A/en
Publication of JPH0531183B2 publication Critical patent/JPH0531183B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/50—Machine control of apparatus for electrographic processes using a charge pattern, e.g. regulating differents parts of the machine, multimode copiers, microprocessor control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

技術分野 この発明はホストCPUと複数のオプシヨン
CPUとの間でのデータ伝送方式に関するもので
ある。 従来技術 たとえば複写機の動作制御を行なうために、マ
イクロコンピユータを用いた、ホスト処理装置
（以下ホストCPUという。）を設けるとともに、
給紙装置や複写倍率設定装置、ペーパーサイズ選
択装置その他の種々の装置毎にマイクロコンピユ
ータを用いたオプシヨンCPUを設ける場合、ホ
ストCPUとオプシヨンCPUとのデータの交信を
行なうために、従来は各オプシヨンCPU別に専
用の回線を設ける方法や、各オプシヨンCPUに
アドレスを割り当てて、アドレス指定によつて所
望のオプシヨンCPUとの交信を行なう方法が知
られている。しかるにこれらの従来のデータ伝送
方式においては、オプシヨンCPUを増設するた
めに、前者は回線を別設しなければならないし、
また後者においては新たなアドレスに対する処理
のためのプログラムの変更などの手間を要するた
めに、ホストCPUを利用したオプシヨンCPUの
増設が困難であるという欠点があつた。さらに上
述の従来の方式においては、各オプシヨンCPU
に高価なインターフエイスが必要であるという欠
点もあつた。 目 的 この発明は上述の欠点を排除して、オプシヨン
CPUにアドレスを付すことを不要とし、ホスト
CPUからアドレスを指定することも不要として
オプシヨンCPUの増設を容易に、かつ安価にな
し得るデータ伝送方式を提供することを目的とす
るものである。 実施例 第１図は本発明を適用した複写機の一例を示す
図であつて、１は複写機本体、２は給紙装置、３
は原稿搬送装置、４はソータである。 次に１０はホストCPU、１１は複写機本体１
の複写制御用のマスタCPU、１２は給紙制御用
の第１オプシヨンCPU、１３は原稿搬送制御用
の第２オプシヨンCPU、１４はソータ制御用の
第３オプシヨンCPUである。なおマスタCPUも
オプシヨンCPUの１つである。 マスタCPU１１と各オプシヨンCPU１２，１
３，１４は第２図或いは第３図に示すように、共
通のデータバス２０を介してホストCPU１０に
データ交信可能に連結される。 マスタCPU１１と各オプシヨンCPU１２〜１
４は送受信可能な装置であり、第２図に詳細に示
すように、ホストCPU１０のクロツクパルス発
生端子はホストCPU１０、マスタCPU１１、オ
プシヨンCPU１２〜１４のクロツクパルス入力
端子に接続され、ホストCPU１０のシリアルア
ウト端子はマスタCPU１１、オプシヨンCPU１
２〜１４のシリアルイン端子に接続され、ホスト
CPU１０のOUT端子はマスタCPU１１、オプシ
ヨンCPU１２〜１４の割込入力端子iNTに接続
される。 一方、マスタCPU１１と各オプシヨンCPU１
２〜１４のシリアルアウト端子はゲート１５−
１，１５−２…を介してホストCPU１０のシリ
アルイン端子に接続される。各ゲート１５−１，
１５−２…は対応するCPU１１，１２，…の制
御出力端子OPから信号“１”が生じたときに開
いて、マスタCPU１１、オプシヨンCPU１２〜
１４のデータをホストCPU１０へ送る。 なお、第３図において、１６Ａ，１６Ｂは追加
可能な送受信可能型のオプシヨンCPU、１７，
１８は表示装置などの受信専用のオプシヨン
CPUである。 ホストCPU１０は第４図に示すように、１サ
イクル期間中に適宜に割り当てられた期間T1〜
T7にそれぞれパルスP1，P2…P7を出力し、これ
を周期Ｔでくり返す。さらにホストCPU１０の
シリアルアウト端子からタイミングT1〜T7に第
５図に示すように、１ビツトのパリテイ信号Ｐ
と、０〜６を示す３ビツトのデータ内容コード
と、実際の情報を示す12ビツトの信号D11〜D0と
で構成される＃０〜＃６のデータブロツクＤをデ
ータバス２０に送出する。これらの＃０〜＃６の
データブロツクＤは相手先のオプシヨンCPUを
特定せずに、各オプシヨンCPUに対して共通の
データバス２０に連続的に送出される。 マスタCPU１１と各オプシヨンCPU１２〜１
４はそれぞれ上記データ内容コードと同じ０〜６
のオプシヨンコードが割り当てられており、伝送
されて来る各データブロツクからその次のデータ
ブロツクが自己のオプシヨンコードに対応するデ
ータ内容コードであることを識別すると、次のデ
ータブロツクを自己のものであると判定して、そ
のデータD11〜D0を読み取るとともに、端子OP
をローレベルとして、ゲート１５−（＝１，
２，３…）を開いて、所定のデータをデータバス
２０を介してCPU１０に送出する。 即ち、たとえばマスタCPU１１については、
オプシヨンコード０と１が付されているデータブ
ロツクが必要であるとすると、このマスタCPU
１１はホストCPU１０から送信されるすべての
データブロツク＃０〜＃６を取り込む一方、デー
タ内容コードを常に監視していて、ホストCPU
１０がタイミングT1とT2に＃０と＃１のデータ
ブロツクを発信すると、たとえばデータ内容コー
ド０のデータをCPU１１が読むと同時に、並び
にデータ内容コード１のデータを読むと同時に
に、ゲート１５−１を開いて、マスタCPU１１
に特有の種々のデータをタイミングT1とT2にホ
ストCPU１０に送る。なお、マスタCPU１１が
２つのデータブロツクを割り当てられているのは
伝送すべきデータが多いためである。 同様にして、第１オプシヨンCPU１２は、タ
イミングT2にホストCPU１０が＃１データブロ
ツクを発信したとき、そのデータ内容のコードが
１であれば次のタイミングT3でコード２がホス
トCPU１０から送信されると判断して次のタイ
ミングT3が自己が発信するデータ送信の期間で
あることを識別し、次いで、第１オプシヨン
CPU１２は、タイミングT3においてホストCPU
１０が＃２データブロツクを発信すると、オプシ
ヨンCPU１２がデータ内容コード２のデータを
読み込むと同時に、ゲート１５−２を開き、第１
オプシヨンCPU１２に特有のデータをホスト
CPU１０に送る。 なおこの発明において、送信と受信の両方が可
能なCPUについては、各データ内容コード毎に
１個のCPUを対応させることによつて、複数の
オプシヨンCPUからデータを同時に発信するこ
とがないようにすることができる。受信のみの
CPUについては他のCPUが使つているデータ内
容コードに対応したデータであつても任意に使用
することは可能である。 上述の動作において、各CPUのデータの送信
と受信とは第６図のように各CPU内に設けた16
ビツトのシリアルシフトレジスタSRにて行なう。 即ちホストCPU１０のOUT端子が“Ｈ”のと
き、マスタCPU１１或いはオプシヨンCPU１２
〜１４の上記シリアルレジスタSRのシリアルア
ウト端子から上記ホストCPU１０のクロツク信
号によつて順次シフトして出力し、またシリアル
イン端子から同様にクロツク信号毎にホスト
CPU１０からのデータを書き込む。そしてホス
トCPU１０のOUT端子が“Ｌ”のとき、各オプ
シヨンCPUは、そのシリアルレジスタSRに書き
込まれたデータを取り込んで演算し、必要に応じ
て新たな16ビツトのデータを該シリアルレジスタ
SRに書き込み、ホストCPUのOUT端子が“Ｈ”
になるのを待つ。なおクロツク信号はホスト
CPU１０に内蔵のものを示したがクロツク発生
手段は外付であつてもよい。 マスタCPU１１あるいはオプシヨンCPU１２
〜１４のゲートの制御方法は、ホストCPUから
送られるデータブロツクから自己のオプシヨンコ
ードに相当する１つ前のデータを読みとつたと
き、次回の通信で送ろうとするデータをシリアル
レジスタにセツトし、次にホストCPU１０の
OUT端子が“Ｈ”となりオプシヨンCPU側で
iNT端子がＨになつたときゲート１５を開いて、
データを送出する。 またオプシヨンCPU間で直接データ伝送はで
きないが、この場合にはオプシヨンCPU→ホス
トCPU→オプシヨンCPUの経路でデータを伝送
できる。 Technical field This invention is based on a host CPU and multiple options.
This relates to the data transmission method between the CPU and the CPU. Prior Art For example, in order to control the operation of a copying machine, a host processing unit (hereinafter referred to as host CPU) using a microcomputer is provided, and
When installing an optional CPU using a microcomputer in each of the paper feeding device, copy magnification setting device, paper size selection device, and other various devices, conventionally each option CPU was A method of providing a dedicated line for each CPU, and a method of allocating an address to each optional CPU and communicating with a desired optional CPU by specifying the address are known. However, in these conventional data transmission methods, in order to add an optional CPU, the former requires a separate line,
The latter also had the disadvantage that it was difficult to add an optional CPU using the host CPU, as it required time and effort to change programs to process new addresses. Furthermore, in the conventional method described above, each option CPU
Another drawback was that it required an expensive interface. Purpose This invention eliminates the above-mentioned drawbacks and provides an optional
It is not necessary to assign an address to the CPU, and the host
The purpose of this invention is to provide a data transmission method that does not require addresses to be specified from the CPU and allows the addition of optional CPUs easily and at low cost. Embodiment FIG. 1 is a diagram showing an example of a copying machine to which the present invention is applied, in which 1 is a copying machine main body, 2 is a paper feeder, and 3
4 is a document conveying device, and 4 is a sorter. Next, 10 is the host CPU, 11 is the copier main body 1
12 is a first option CPU for paper feed control, 13 is a second option CPU for document conveyance control, and 14 is a third option CPU for sorter control. Note that the master CPU is also one of the optional CPUs. Master CPU11 and each option CPU12,1
3 and 14 are connected to the host CPU 10 via a common data bus 20 for data communication, as shown in FIG. 2 or 3. Master CPU11 and each option CPU12~1
4 is a device capable of transmitting and receiving, and as shown in detail in FIG. 2, the clock pulse generation terminal of the host CPU 10 is connected to the clock pulse input terminals of the host CPU 10, master CPU 11, and optional CPUs 12 to 14, and the serial out terminal of the host CPU 10 is master CPU11, option CPU1
Connected to serial in terminals 2 to 14, host
The OUT terminal of the CPU 10 is connected to the interrupt input terminals iNT of the master CPU 11 and optional CPUs 12 to 14. On the other hand, master CPU 11 and each option CPU 1
Serial out terminals 2 to 14 are connected to gate 15-
1, 15-2, . . . are connected to the serial in terminal of the host CPU 10. Each gate 15-1,
15-2... is opened when a signal "1" is generated from the control output terminal OP of the corresponding CPU 11, 12,..., and the master CPU 11, option CPU 12~
14 data is sent to the host CPU 10. In addition, in FIG. 3, 16A and 16B are optional CPUs that can be added to transmit/receive, 17,
18 is a reception-only option such as a display device
It is the CPU. As shown in FIG. 4, the host CPU 10 operates during a period T 1 to appropriately allocated during one cycle period.
Pulses P 1 , P 2 . . . P 7 are outputted at T 7 , respectively, and this is repeated at a period T. Furthermore, as shown in FIG. 5, a 1-bit parity signal P is sent from the serial out terminal of the host CPU 10 at timings T1 to T7 .
, a 3-bit data content code indicating 0 to 6, and 12-bit signals D 11 to D 0 indicating actual information, and sends data block D #0 to #6 to the data bus 20. . These data blocks D #0 to #6 are continuously sent to the common data bus 20 to each option CPU without specifying the destination option CPU. Master CPU11 and each option CPU12~1
4 is the same as the data content code above, 0 to 6.
Option code is assigned, and if it identifies from each transmitted data block that the next data block has a data content code corresponding to its own option code, it assigns the next data block as its own. It is determined that the data D 11 to D 0 is read, and the terminal OP is
is set to low level, gate 15-(=1,
2, 3...) and sends predetermined data to the CPU 10 via the data bus 20. That is, for example, regarding the master CPU 11,
If data blocks with option codes 0 and 1 are required, this master CPU
11 captures all data blocks #0 to #6 sent from the host CPU 10, and constantly monitors the data content code.
When the CPU 10 transmits data blocks #0 and #1 at timings T1 and T2 , for example, at the same time as the CPU 11 reads the data with the data content code 0, and at the same time as the data with the data content code 1, the gate 15 -1 and master CPU11
various data specific to the host CPU 10 at timings T1 and T2 . Note that the reason why the master CPU 11 is assigned two data blocks is because there is a large amount of data to be transmitted. Similarly, when the host CPU 10 transmits #1 data block at timing T2 , if the code of the data content is 1, the first option CPU 12 transmits code 2 from the host CPU 10 at the next timing T3 . It determines that the next timing T3 is the period for transmitting data, and then selects the first option.
The CPU 12 is connected to the host CPU at timing T3 .
10 transmits the #2 data block, the optional CPU 12 reads the data of data content code 2, opens the gate 15-2, and transmits the first data block.
Hosts data specific to option CPU12
Send to CPU10. In addition, in this invention, for CPUs that can both send and receive data, by associating one CPU with each data content code, it is possible to prevent data from being sent from multiple optional CPUs at the same time. can do. reception only
Regarding the CPU, it is possible to arbitrarily use data even if it corresponds to the data content code used by other CPUs. In the above-mentioned operation, the data transmission and reception of each CPU is performed by the 16
This is done using a bit serial shift register SR. That is, when the OUT terminal of the host CPU 10 is “H”, the master CPU 11 or the optional CPU 12
The clock signal of the host CPU 10 is sequentially shifted and output from the serial out terminal of the serial register SR of 14 to 14, and the clock signal is output from the serial in terminal of the host CPU 10 in the same manner.
Write data from CPU10. Then, when the OUT terminal of the host CPU 10 is "L", each option CPU takes in the data written to its serial register SR, performs calculations, and writes new 16-bit data to the serial register as necessary.
Write to SR, host CPU OUT pin becomes “H”
wait until it becomes Note that the clock signal is from the host
Although a built-in clock generating means is shown in the CPU 10, the clock generating means may be externally attached. Master CPU11 or optional CPU12
The control method for gates 14 to 14 is that when the previous data corresponding to the own option code is read from the data block sent from the host CPU, the data to be sent in the next communication is set in the serial register, Next, host CPU10
The OUT terminal becomes “H” and the optional CPU side
When the iNT terminal becomes H, gate 15 is opened,
Send data. Also, although direct data transmission between optional CPUs is not possible, in this case data can be transmitted via the route from optional CPU to host CPU to optional CPU.

【表】 パリ 〓【table】 Paris 〓

Claims (1)

【特許請求の範囲】 １ ホストCPUと、送受信可能な複数のオプシ
ヨンCPUとの間でデータ伝送を行うとともに、
受信専用のオプシヨンCPUの増設が可能なデー
タ処理システムにおけるデータ伝送方法であつ
て、 上記ホストCPUの通信用バスラインに、アド
レスを付さない複数のオプシヨンCPUの通信用
バスラインを共通接続し、 上記ホストCPUは上記バスラインに、上記複
数のオプシヨンCPUに対して伝送すべきすべて
のデータを、データの内容毎に所定数ビツトを単
位とする複数のデータブロツクに分割し、かつ、
上記各データブロツクにデータの内容を示すコー
ドを付して、順次所定周期で繰り返して送出し、 上記複数のオプシヨンCPUは、それぞれ上記
ホストCPUから上記バスラインに送られる各デ
ータブロツクを受信し、上記受信した各データブ
ロツクに付された上記コードに基づいて、自己に
必要なデータを識別して当該識別したデータに関
する所定の処理を実行するとともに、 上記複数のオプシヨンCPUに含まれる送受信
可能なオプシヨンCPUは、上記受信した各デー
タブロツクに付された上記コードに基づいて、他
の送受信可能なオプシヨンCPUと重複しないよ
うに自己に予め割り当てられたデータ送信の期間
を識別して、上記識別された期間内に自己の送出
データを上記バスラインに送出し、 受信専用のオプシヨンCPUが増設された際に
は、上記増設された受信専用のオプシヨンCPU
は、上記ホストCPUから上記バスラインに送ら
れる各データブロツクを受信し、上記受信した各
データブロツクに付された上記コードに基づい
て、上記受信専用のオプシヨンCPUが増設され
る前に既に設けられたオプシヨンCPUによつて
所定の処理が実行されるデータと重複するように
予め割り当てられた自己に必要なデータを識別し
て、当該識別したデータに関する所定の処理を実
行することを特徴とするデータ伝送方法。[Claims] 1. Data transmission between a host CPU and a plurality of optional CPUs capable of transmitting and receiving,
A data transmission method in a data processing system in which an optional reception-only CPU can be added, wherein the communication bus lines of a plurality of optional CPUs without addresses are commonly connected to the communication bus line of the host CPU, The host CPU divides all data to be transmitted to the plurality of optional CPUs onto the bus line into a plurality of data blocks each having a predetermined number of bits for each data content, and
A code indicating the content of the data is attached to each of the data blocks, and the code is sent out repeatedly at a predetermined cycle, and each of the plurality of optional CPUs receives each data block sent from the host CPU to the bus line, Based on the code attached to each received data block, it identifies the data it needs and executes a predetermined process regarding the identified data. Based on the code attached to each received data block, the CPU identifies a data transmission period that is pre-assigned to itself so as not to overlap with other optional CPUs that can send and receive data, and Sends its own transmission data to the above bus line within the period, and when a receive-only optional CPU is added, the above-mentioned received receive-only optional CPU
receives each data block sent from the host CPU to the bus line, and based on the code attached to each received data block, determines whether the received data block has already been installed before the reception-only optional CPU is added. Data characterized by identifying necessary data that is allocated in advance so as to overlap with data on which a predetermined process is executed by the optional CPU, and executing a predetermined process on the identified data. Transmission method.
JP58003040A 1983-01-11 1983-01-11 Data transmitting system Granted JPS59127133A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP58003040A JPS59127133A (en) 1983-01-11 1983-01-11 Data transmitting system
FR8400216A FR2539260B1 (en) 1983-01-11 1984-01-09 DATA TRANSMISSION SYSTEM
DE19843400464 DE3400464A1 (en) 1983-01-11 1984-01-09 DATA TRANSFER SYSTEM
US07/062,562 US4847756A (en) 1983-01-11 1987-06-12 Data transmission system for a computer controlled copying machine having master and slave CPU's

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58003040A JPS59127133A (en) 1983-01-11 1983-01-11 Data transmitting system

Publications (2)

Publication Number Publication Date
JPS59127133A JPS59127133A (en) 1984-07-21
JPH0531183B2 true JPH0531183B2 (en) 1993-05-11

Family

ID=11546193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58003040A Granted JPS59127133A (en) 1983-01-11 1983-01-11 Data transmitting system

Country Status (4)

Country Link
US (1) US4847756A (en)
JP (1) JPS59127133A (en)
DE (1) DE3400464A1 (en)
FR (1) FR2539260B1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523299A (en) * 1982-09-21 1985-06-11 Xerox Corporation Message transmitting system for reproduction machines and copiers
JPH063908B2 (en) * 1985-03-05 1994-01-12 ソニー株式会社 Data transmission method
JPS61211728A (en) * 1985-03-15 1986-09-19 Sony Corp Data processor
US4811052A (en) * 1985-08-08 1989-03-07 Canon Kabushiki Kaisha Control device for control of multi-function control units in an image processing apparatus
JPS6235977A (en) * 1985-08-08 1987-02-16 Canon Inc Controller for image forming device
US5193159A (en) * 1986-09-24 1993-03-09 Hitachi, Ltd. Microprocessor system
JP2619416B2 (en) * 1987-09-24 1997-06-11 株式会社日立製作所 emulator
JPH01161566A (en) * 1987-12-18 1989-06-26 Hitachi Ltd Data processing system of decentralized processing system
US5251295A (en) * 1988-07-11 1993-10-05 Minolta Camera Kabushiki Kaisha Image processing system having slave processors for controlling standard and optional modules
US5191648A (en) * 1988-07-11 1993-03-02 Minolta Camera Kabushiki Kaisha Image processing system
US5138701A (en) * 1988-07-12 1992-08-11 Minolta Camera Kabushiki Kaisha Data communication control system
EP0389175A3 (en) * 1989-03-15 1992-11-19 Fujitsu Limited Data prefetch system
IT1232090B (en) * 1989-05-04 1992-01-23 Sgs Thomson Microelectronics CONNECTION SYSTEM BETWEEN A MAIN PROCESSING UNIT AND THE PERIPHERAL UNITS
IT1232089B (en) * 1989-05-04 1992-01-23 Sgs Thomson Microelectronics COMMUNICATION SYSTEM BETWEEN A MAIN PROCESSING UNIT AND PERIPHERAL UNITS
US5086427A (en) * 1990-04-09 1992-02-04 Unisys Corporation Clocked logic circuitry preventing double driving on shared data bus
JPH03295495A (en) * 1990-04-13 1991-12-26 Toshiba Corp Timer device
US5130806A (en) * 1990-09-28 1992-07-14 Xerox Corporation Job comment/operator messages for an electronic reprographic printing system
US5276900A (en) * 1990-12-14 1994-01-04 Stream Computers Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto
US5339168A (en) * 1991-12-31 1994-08-16 Xerox Corporation Copier/duplicator network
US5694323A (en) * 1995-04-04 1997-12-02 Persyst, Inc. Monitoring system with particular application to monitoring a cash-basis operation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS497937A (en) * 1972-04-10 1974-01-24
JPS4979137A (en) * 1972-12-01 1974-07-31
JPS49114846A (en) * 1973-02-28 1974-11-01
JPS512363A (en) * 1974-03-26 1976-01-09 Hitachi Ltd
JPS5324238A (en) * 1976-08-18 1978-03-06 Nec Corp Data processing system for display system

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE253555C (en) *
US3310782A (en) * 1963-02-27 1967-03-21 Ultronic Systems Corp Data message system
US3340516A (en) * 1965-04-27 1967-09-05 Ibm Master-slave net control
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
DE2259223A1 (en) * 1972-12-04 1974-06-27 Licentia Gmbh CIRCUIT ARRANGEMENT TO CONNECT A MORE NUMBER OF BINARY INFORMATION SUBMITTING DEVICES THAN RECORDING DEVICES
DE2546202A1 (en) * 1975-10-15 1977-04-28 Siemens Ag COMPUTER SYSTEM OF SEVERAL INTERCONNECTED AND INTERACTING INDIVIDUAL COMPUTERS AND PROCEDURES FOR OPERATING THE COMPUTER SYSTEM
US4188668A (en) * 1976-10-04 1980-02-12 International Business Machines Corporation Computer-controlled copier-printers
US4124887A (en) * 1977-04-04 1978-11-07 Universal Instruments Corporation Real time computer control system for automatic machines
US4170791A (en) * 1977-08-30 1979-10-09 Xerox Corporation Serial data communication system for a reproduction machine
US4314334A (en) * 1977-08-30 1982-02-02 Xerox Corporation Serial data communication system having simplex/duplex interface
US4128883A (en) * 1977-09-30 1978-12-05 Ncr Corporation Shared busy means in a common bus environment
US4161786A (en) * 1978-02-27 1979-07-17 The Mitre Corporation Digital bus communications system
US4209840A (en) * 1978-06-28 1980-06-24 Honeywell Inc. Data processing protocol system
US4413341A (en) * 1978-06-28 1983-11-01 Markhasin Alexandr B Method for exchange of data between central station and peripheral stations
US4241398A (en) * 1978-09-29 1980-12-23 United Technologies Corporation Computer network, line protocol system
US4304001A (en) * 1980-01-24 1981-12-01 Forney Engineering Company Industrial control system with interconnected remotely located computer control units
GB2070302B (en) * 1980-02-19 1985-02-13 Omron Tateisi Electronics Co Data communication system
US4298860A (en) * 1980-03-10 1981-11-03 Control Data Corporation Monitor and control apparatus
US4368514A (en) * 1980-04-25 1983-01-11 Timeplex, Inc. Multi-processor system
JPS5764749A (en) * 1980-10-09 1982-04-20 Canon Inc Control method and device of copying machine
GB2079004B (en) * 1980-06-03 1985-04-03 Canon Kk Reproduction apparatus
US4365297A (en) * 1980-12-29 1982-12-21 Forney Engineering Company Industrial control system with distributed computer implemented logic
US4417336A (en) * 1981-06-18 1983-11-22 The Bendix Corporation Method of testing with computers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS497937A (en) * 1972-04-10 1974-01-24
JPS4979137A (en) * 1972-12-01 1974-07-31
JPS49114846A (en) * 1973-02-28 1974-11-01
JPS512363A (en) * 1974-03-26 1976-01-09 Hitachi Ltd
JPS5324238A (en) * 1976-08-18 1978-03-06 Nec Corp Data processing system for display system

Also Published As

Publication number Publication date
FR2539260B1 (en) 1992-10-23
DE3400464A1 (en) 1984-07-12
DE3400464C2 (en) 1993-04-22
US4847756A (en) 1989-07-11
JPS59127133A (en) 1984-07-21
FR2539260A1 (en) 1984-07-13

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