SU955013A1 - Device for interfacing computer to peripheral devices - Google Patents

Description

(5) DEVICE FOR PAIRING A DIGITAL COMPUTING MACHINE WITH PERIPHERAL DEVICES

The invention relates to computing and can be used in information-measuring systems, in which the interconnection of devices is carried out through a common bus. A device for interfacing a digital computer with peripheral devices is known, comprising an interrupt block, an instruction register, an address register, a state block, a control block, and an adder SP. However, such a device contains circuits in accordance with specific functions, which complicates the device. The closest to the present invention is a device for interfacing a digital computer with peripheral devices, containing a communication unit with a digital computer, the input-output group of which is connected to the first group of input-output devices of the device, the communication unit with peripheral devices, the input-output group of which connected to the second group of input-output devices, the decoder, the first and second outputs of which are connected respectively to the first inputs of the control unit and the register, the parity forming unit, the decoder input connected to the first output a communication unit with a digital computer, the second output of which is connected to the second input of the register, the first output of which is connected to the first input of the communication unit with a digital computer, and the first output and second input of the control unit are connected respectively to the second input and to the third output of the communication unit to the digital computer 2. A disadvantage of the known device is the need for a large amount of equipment. The purpose of the invention is to simplify the device. This goal is achieved by introducing a switch into the device, the first, second and third triggers, with the first output of the communication unit with peripheral devices connected to the first inputs of the switch and the third trigger, the output of which is connected to the third input of the communication unit with a digital computer, the fourth and the fifth outputs of which are connected to the first inputs of the first and second triggers, the output of the second trigger is connected to the first input of the communication unit with peripheral devices, the second output of which is connected to the second input of the switch, the third output of the second Istra is connected to the third input of the switch, the fourth input of which is connected to the second input of the third trigger and with the output of the first trigger whose second input is connected to the second input of the second trigger and the third output of the decoder, the fourth output of which is connected to the fifth input of the switch, output which is connected to the fourth we enter the communication unit with a digital computer. In addition, the element And is entered into the device. The first input of the element I is connected to the fourth output of the decoder, the fifth output of the communication unit with peripheral devices is connected to the second input of the element And, the output of which is connected to the fifth input of the communication unit with a digital computer . Such a construction device allows

It greatly reduces hardware costs.

The drawing shows a diagram of the proposed device.

The device contains a block of communication with a digital computer, a block 2 of communication with peripheral devices, a decoder 3, a register 4, a switch 5 a control block 6, a first trigger 7, a second trigger 8, a third trigger 9 a parity generating block 10, element 11, inputs 12 and 13, outputs 14 and 15, input 16, outputs inputs 20 and 21 of communication unit 1 with a digital computer, output 22, inputs 23 and 24, outputs 25-27, inputs 28 and 29, outputs 30 and 31 of communication unit 2 with peripheral devices, the outputs 32-35 of the decoder 3, the outputs 36 and 37 of the register 4, the output 3V of the first trigger 7, the output 39 of the control unit 6, the groups 40 and .41 of the device's input-outputs.

The device works as follows.

Programmatic information exchange between the main memory of the digital computer and peripheral devices is carried out under the control of the digital computer program. When working in software mode

having received this signal, it completes the operation on the common bus.

If the peripheral device register is accessed, block 3 decrypts the address of this peripheral device received from outputs 14 and triggers output 6 to block 6. Block 6 enables output of command code and peripheral number in register 4 by output signal 39. In this case, the block 6 by the signal on the input 24 through the block 2 informs the peripheral device about the readiness of the received information to be transmitted to the peripheral device. The command and status register and the peripheral data register are implemented on a common 8-bit shift register. The direction of information transfer between the interface device and the peripheral devices is determined by the signal. The direction of the output 25 of the communication unit 2 with the peripheral devices. Signal Zero Signal Direction means the transfer of information from the interface device, one - to the device from the device used two, addressed from the common bus, register A: command and status register, data register. Programmatically download and read information from addressable registers. Any one of them is addressed as follows. The processor places a register address on the line, and a read or write code on the line of the operation code. If recording is being performed, download information is set up on the data line. After that, the synchronization system of the common bus is set. Unit 3 decrypts the address and operation code of the common bus entering it from output 14 and exposes the corresponding signal at the register access output 35. When writing, the information in register 4 comes from the outputs 19 of unit 1, when reading information from register 4 it goes to the first group of inputs-outputs 40 at input 20 and through switch 5 at input 21. Unit 3 signals unit 6 to perform an operation on output 32, after which unit 6 generates a response clock signal, which is “on the first group of input-outputs 40 from input 13. Processor, 5 peripherals th device. Single signal value The end of the operation on output 26 of block 2 indicates that the peripheral device is not working and is waiting for a command from the PC process. In order to transmit the command code entered in register k to the peripheral device, it is necessary that the signal Direction on output 25, block 2 is zero, and the signal End of operation on output 26 of the unit is single. Peripheral device in response to a signal. Control on input 2 of block 2 generates a pulse signal. Shift on output 30 of block 2, which converts the information recorded 8. parallel code in register k to serial. Serial and formation from output 37 of register A, passing through parity forming unit 10, is fed to input 29 of unit 2 to a peripheral device that generates 8 pulse signals. Shift output 30 of unit 2 to receive the command code and parity bit to control the transmission of information. After that, the peripheral device sets a zero signal. End of operation on output 2b of block 2 and generates a single signal. Requirement on output 27 of block 2, which goes to block 6 of control. Signal 39 resolves parallel loading of information on output 19 of block 1 to register C via data lines, and signal on input 2k of block 2 to the peripheral device informs about readiness of information for transmission. The peripheral device again generates 9 Shift signals to receive a byte of information and sets up a Demand signal. This exchange occurs until 128 bytes of information are transmitted or a signal is received from the processor. End of data block at input 18 of block 1 and synchronization signal at output 3 of decoder 3- The state of the second trigger 8 is analyzed by the peripheral device at input 28 of block 2 At the end of the exchange, the peripheral device exposes a single signal. The end of the operation on output 26 of block 2. If the command code sets the transfer of information from the peripheral device to the processor, then the peripheral device generates a single 36 si nal direction po.vyhodu 25 unit 2, which blocks outlet 10 parity forming unit 39 for output unit 6 allows the sequential conversion of information coming-out unit 31 2, in parallel to register i. In this case, the peripheral device generates 8 pulse signals Shift. The information generated by a parallel code with four bits from the register at input 20 of block 1 and four bits at input 21 through switch 5 is transmitted to the processor via data lines. At the same time, a zero signal is generated at the output 33 of the decoder 3, which allows the transfer of information from the register at output 36 through the switch 5. Before transmitting the next byte, the peripheral device generates a single signal. Requirement for output 27 of block 2 if one more byte is to be sent, or a single signal End of operation on exit 26 of block 2, if the operation has been completed. In the automatic request processing mode, the device works as follows. The first trigger 7 is installed by software from the digital computer via 3 decoder 3- If the peripheral device has completed the execution of a given command, then it generates a single signal. End of operation on output 2b of unit 2. Unit signal End of operation and a single signal at output 38 of the first trigger 7 are set to the single state is the third trigger 9, the output of which through the block 1 on the input 16 performs processor interruption, informing it in such a way that the peripheral device has completed the execution of the specified command. Peripheral devices are reset to the initial state by the signal Reset on input 23 of unit 2 produced by control unit 6. In this case, the processor generates a general or software reset on the output 15 of block 1, which is fed to the block 6 of the control. The signal from output 33 of decoder 3 to the processor through switch 5, output 21 of unit 1 transmits state prisks: signal End of operation on input 26, signal Requirement for output 27 of unit 2 and the status of the first even parity trigger 7 Block 10 agnostic and fault localization Symptom An error is output through the element I P to the input 12 of the communication unit 1 with a digital computer, which comes from the peripheral device through the 22 unit 2 communication with the peripheral devices to interface to reduce it. data buffering block, imitation mode setting block, imitation mode control block, peripheral state memory block, time interval control block and autonomous check block, Reduction of equipment is achieved by using the command and status register, the data register is implemented on one shift register re. The deceptive signal for the shift register information is the signal end of the operation. In the case of a single signal state. The end of the operation is transmitted to the peripheral device by the command code, with zero or from the peripheral device, the data or status codes. Sequential transmission of command and data codes between the interface device and the peripheral devices allows a significant reduction in the number of communication signal boosters. The use of bi-directional bus drivers on the data lines allows connection of the interface device to the minimum bus interface. The invention The device for interfacing a digital computer with peripheral devices, comprising a decoder, a register, a control unit, a parity generating unit, the communication unit of a digital computer connected to the first group of inputs of the device outputs, a communication unit with peripheral devices connected to the second group of inputs -outputs of the device, the first and second outputs of the decoder are connected respectively to the first inputs of the control unit and the horn register, the input of the decoder is connected to the first input of the communication unit with a digital computer, the second output of which It is connected to the second register 8 IN, the first output of which is connected to the first input of the communication unit with a digital computer, the first output and the second input of the control unit are connected respectively to the second input and to the third output of the central electronic communication block, the third and fourth inputs of the block C with peripheral devices connect: not to the third and fourth outputs of the control unit, the third, fourth and fifth inputs. Which are connected respectively to the first, second and third outputs of the communication unit with peripheral devices, the third and fourth outputs and the second input first connected to the second and third inputs and output of the parity generator, the first and third inputs of which are connected respectively to the second output and fourth register input, the third input of which is connected to the second output of the control unit, the sixth output of the communication unit with peripheral devices connected to p The second input of the register, characterized in that, in order to simplify the device, a switch, the first, second and third triggers are entered into it, the first output of the communication unit with peripheral devices connected to the first the inputs of the switch and the third trigger, whose input is connected to the third input of the communication unit with a digital computer, the fourth and fifth outputs of which are connected to the first inputs of the first and second triggers, the output of the second trigger to the first input of the communication unit with peripheral devices, the second the output of which is connected to the second input of the switch; the third output of the register is connected to the third input of the switch; the fourth input of which is connected to the second input of the third trigger and to the output of the first trigger, the second input of which is connected to the second th input of the second flip-flop and a third output of the decoder, a fourth output is connected to a fifth input of the switch whose output is coupled to a fourth input of the communication with the digital computer. 2. The device according to claim 1, that is, that an element I is inserted into it, the first input of the element I is connected to the fourth output of the decoder, the fifth output of the communication unit with peripheral devices is connected to the second input element And, the output of which is connected to the fifth input of the communication unit, Sources of information taken into account in the examination 1. US patent number 3815099, cl. G About F 3/0, publ. 19772. USSR author's certificate No. 561180, class C. On F3 / 0.1975 (prototype).

Claims (2)

¹ claims A device for interfacing a digital computer with peripheral devices, comprising a decoder, a register, a control unit, a parity unit, the communication unit with a digital computer connected to the first group of inputs and outputs of the device, the communication unit with peripheral devices connected to the second group of inputs and outputs of the device, the first and second the decoder outputs are connected respectively to the first inputs of the control unit and the register, the decoder input is connected to the first input of the communication unit with a digital computer, the second output of which is connected to the second m the register input, the first 'output of which is connected to the first input of the communication unit with the digital computer, the first output and the second input of the control unit are connected respectively to the second input and use them to be the output of the communication unit with the digital computer, the fourth and fourth inputs of the communication unit> 5013 - 8 s peripheral devices are connected to the third and fourth outputs of the control unit, the third, fourth and fifth inputs. of which are connected to ₅ respectively with the first, second and third outputs of the communication unit with peripheral devices, the third and fourth outputs and the second input of which are connected respectively, with the second te and the third inputs and the output of the parity block, the first and third inputs of which are connected respectively to the second output and the fourth input of the register, the third input of which 15 is connected to the second output of the control unit, the sixth output of the communication unit with peripheral devices is connected to the fifth an input of the register, which, ^{in order to} simplify the device, ^{includes a} switch, first, second and third triggers, the first output of the communication unit with peripheral devices being connected to the first inputs the switch and the third trigger, the input of which is connected to the third input of the communication unit with a digital computer, the fourth and fifth outputs of which are connected to the first inputs of the first and second triggers, the output of the second 'trigger is connected to the first input of the communication unit with peripheral devices, the second output of which is connected to the second input of the switch, the third output of the register is connected to the third input of the switch? the fourth input of which is connected to the second input of the third trigger and the output of the first trigger, the second input of which is connected to the second input of the second trigger and the third output of the decoder, the fourth output of which is connected to the fifth input of the switch, the output of which is connected to the fourth input of the communication unit with the digital computer . 2. The device according to p. with the second input of the element And, the output of which is connected to the fifth input of the communication unit c, a digital computer.