KR0174853B1 - Asynchronous Serial Communication Transmit / Receive Device Between Two Processors Using Other Memory - Google Patents

Abstract

The present invention relates to an apparatus used to transmit various types of data formats by asynchronous serial communication method between two processors in a communication system using a memory of a counterpart, and a wait method when transmitting data using a memory of the counterpart. Will be used. It is an asynchronous serial communication method using memory, which is composed of a small number of lines, which is economical due to the reduction of the required drive, and also has the convenience of physical use, and the other memory can be used as its own memory. It provides the logical convenience of the parallel communication method.

Description

Asynchronous Serial Communication Transmit / Receive Device Between Two Processors Using Other Memory

1 is a block diagram of an asynchronous serial communication transmission / reception apparatus between two processors using a counterpart memory of the present invention.

2 is a structural diagram showing a mode setting address map of an asynchronous direct communication transmitting / receiving device between two processors using a counterpart memory;

3 is a structural diagram showing the data format between the processor B of FIG. 1 and the apparatus of the present invention;

(a) is a structural diagram showing the TXD data format when writing.

(b) is a structural diagram showing the TXD data format at the time of read.

(c) is a structural diagram showing TXD data format when using MODE.

(d) shows the structure of RXD data format in steady state.

(e) is a structural diagram showing RXD data format in the case of TXD parity error.

4 is a timing diagram of signals made between processor A and the apparatus of the present invention when processor A in FIG. 1 writes data to processor B. FIG.

FIG. 5 is a timing diagram of signals generated between processor A and the apparatus of the present invention when processor A in FIG. 1 reads data of processor B. FIG.

* Explanation of symbols for main parts of the drawings

1: Mode register 2: Address register

3: Transmission data register 4: Way register

5: 1st logical gate 6: 1st counter

7: second counter 8: parity generator

9: second logic gate 10: parallel / serial register

11: Serial / Parallel Register 12: Parity Check Register

13: error pattern detector 14: line drive

15: line receive

The present invention relates to an apparatus used for transmitting data by asynchronous serial communication method between two processors using a memory of a counterpart in a communication system, and using a WAIT as a communication method when using a counterpart's memory. A device for asynchronous serial communication transmission and reception between processors.

Conventionally, serial or parallel communication has been performed when transferring data between processors. However, in the case of serial communication, there is an advantage in that data can be transmitted over a long distance with a small number of lines, but there is a disadvantage in that its use is limited due to the limitation of the transmission speed. On the other hand, in the case of parallel communication, the transmission speed is faster than the serial communication, and the use thereof is easy, while there are disadvantages in that many wire lines are required and many drives are required when transmitting at a long distance.

The present invention is to solve the above-mentioned conventional problems, it is possible to write or read the data of the desired address of the counterpart processor, such as parallel communication, and also requires a small number of lines and a small number of drives, such as serial communication to a long distance The data can be transferred.

1 is a block diagram of an asynchronous serial communication transmitting / receiving device between two processors using a counterpart memory of the present invention. The mode register 1, the address register 2, and the transmission data register are shown in FIG. (3), the wait register (4), the first logic gate (5), the first counter (6), the second counter (7), the parity generator (8), the second logic gate (9) ), Parallel / serial register 10, serial / parallel register 11, parity check register 12, error pattern detector 13, line drive 14, and line receive 15. It is configured to include.

That is, the processor B and the chip select signal (/ CS), read signal (/ RD), write signal (/ WR), address signal (ADDRESS), data signal (DATA), and CPU clock signal (CPUCLK) for data transmission / reception. Processor A for selectively outputting a signal, and receiving a reset signal (/ RESET), a weight signal (/ WAIT), an error signal (/ ERR), or the like; A mode register 1, an address register 2, a transmission data register 3 and a chip register signal / CS, a read signal / RD and a write signal / WR of the processor A ; Parallel / serial for transmitting the data format to the line drive 14 in synchronization with the clock signal CLK supplied from the mode register 1, the address register 2 and the transmission data register 3 from the outside. Register 10; A line drive 14 for transmitting the data format transmitted from the parallel / serial register 10 to the processor B; A parity generator 8 for generating parity bits falling into the lowest part of the data format; A wait register (4) for selectively receiving the input data value and providing a time delay and a reset signal (/ RESET) to the processor A, and outputting the value to the first counter 6; A first counter 6 that counts the CPU clock signal to produce a weight signal; A line receiver 15 for transmitting the data of the processor B to the processor A; A serial / parallel register for dividing the data format input through the line receive 15 into a data portion and a parity bit portion, and outputting data to the processor A and parity bits to the parity check register 12 through the data line. 11); A parity check register 12 which detects whether an error has occurred in the parity bit transmitted from the serial / parallel register 11 and outputs it to the second logic gate 9; An error pattern detector (13) for checking whether an error has occurred in the data format input through the line receive (15); A second logic gate 9 for logically calculating this value and outputting an error signal / ERR to the processor A when an error signal is transmitted from the parity check register 12 and the error pattern detector 13; A second counter 7 which receives the mode register 1, the output signal of the wait register 4 and the CPU clock signal CPUCLK, and outputs them to the first logic gate 5; And a first logic gate 5 which logically performs an input of the first counter 6 and the second counter 7 and outputs a weight signal / WAIT to the processor A.

FIG. 2 is a structural diagram showing a mode setting address map of an asynchronous serial communication transmitting / receiving device between two processors using a counterpart memory. The address inputted to the mode register 1 of FIG. 1 and the signal at read time (/ RD) are shown in FIG. And the mode address area determined by the signal at write (/ WR), that is, the data area 21 of the transmission (/ WR = 0) and the reception (/ RD = 0) and the wait register area 22. ) And an area from the mode 0 area 23-0 to the mode n area 23-n.

3 is a structural diagram showing the data format for data communication between the processor B of FIG. 1 and the asynchronous serial communication transmitting / receiving apparatus between two processors using the counterpart memory of the present invention, and (A) shows a line drive signal during write. (TXD) is a structural diagram showing the data format, which is a data format transmitted when the data processed by the processor A is to be stored in the memory of the processor B.

On the other hand, (B) is a structural diagram showing the data format of the line drive signal (TXD) at the time of the read (READ), which is a data format for specifying the address of the processor B memory to read data stored in the memory of the processor B to be. On the other hand, (C) is a structural diagram showing the data format of the line drive signal (TXD) when using the mode (MODE), which is a data format for specifying the mode to be used by the processor A. On the other hand, (D) is a structural diagram showing the data format of the line receive (RXD) in the steady state, which is the data format output from the processor B the data of the address requested by the processor A. On the other hand, (E) is a structural diagram showing the line receive (RXD) data format at the time of the parity error of the line drive signal TXD.

That is, in each of the above cases, the data format of the line drive signal TXD in the write mode after the initial start bit input as shown in (a) is shown in order of mode, address, data, and parity bits. Likewise, the mode, address, and parity bits of the line drive signal TXD are sequentially displayed during the read operation.

On the other hand, as shown in (c), when the mode is used, the data format of the line drive signal TXD is displayed in the order of mode and parity bits.In the case of (d), the line format of the RXD is Data and parity bits appear sequentially, and as shown in (e), an error pattern appears in the data format of the line receive RXD when a parity error of the line drive signal TXD occurs.

FIG. 4 is a timing diagram of signals generated between processor A and the asynchronous serial communication transmission / reception apparatus using the counterpart memory of the present invention when processor A of FIG. 1 writes data to processor B. FIG. Changes in the level of the chip select signal (/ CS), the write signal (/ WR), the address signal (ADDRESS), the data signal (DATA) and the weight signal (/ WAIT) according to the change of the CPU clock signal (CPUCLK) are shown. In the timing diagrams of the address signal ADDRESS and the data signal DATA, portions represented by the rectangles in the lower center of the address represent useful address areas and useful data areas, respectively.

FIG. 5 is a timing diagram of signals generated between processor A and an asynchronous serial communication transmitter / receiver between two processors using the counterpart memory of the present invention when processor A of FIG. ), The level change of the chip selection signal / CS, read signal / RD, address signal ADDRESS, data signal DATA, line receive signal RXD, and weight signal / WAIT It was.

When writing data from the processor A to the processor B of FIG. 1, first, the state of the chip select signal / CS and the write signal / WR becomes 'low' state as shown in the timing diagram of FIG. Is in the transmit / receive data area 21 of FIG. 2, the WRITE MODE value is input to the mode register 1. At the same time, the address value is input to the address register 2, and the data value in the data line is input to the transmission data register 3.

If the CPU speed of processor A is faster than the access timing of the asynchronous serial communication transmitter / receiver between the two processors using the counterpart memory of the present invention, the number of CPU clock signals CPUCLK to be weighted is shown in the wait register region 22 of FIG. It inputs to the wait register 4 of FIG. The reset value of this wait register 4 becomes the maximum value of this register.

The address value and the data value are delayed by the value of the wait register 4 and input to the address register 2 and the transmission data register 3.

Information inputted to the mode register 1, the address register 2, and the transmission data register 3 is inputted by the parallel / serial register 10 to the line drive signal TXD at the time of the write WRITE shown in FIG. Like the data format, it consists of the mode, address, data, and parity bits, and the parallel value of the register becomes a serial value line drive (TXD) and is output to the processor B.

At this time, the information input to the parallel / serial register 10 adds the parity bit generated by the parity generator 8 to the lowest part of the data format.

The data output from the parallel / serial register 10 is sent using the line drive 14 to drive a long distance.

On the other hand, when the processor A wants to read data stored in the memory of the processor B, first, as shown in the timing diagram of FIG. 5, the state of the chip select signal / CS and the read signal / RD is' The read mode value is input to the mode register 1 when the address is in the low 'state and the address value is in the middle of the transmit / receive data area of FIG. At this time, the value in the address line is input to the address register 2.

At this time, the weight signal is set to a 'low' state regardless of the value of the weight register 4, and the line receive signal RXD of FIG. 5 is input through the line receive 15. When the line receive signal RXD has a data format in the normal state of FIG. 3, the start bit at this time is input to the second counter 7 of FIG. When the line receive signal RXD is input to the serial / parallel register 11 and parallel data is separated into serial data, the / WAIT signal is made 'low' to 'high'. At this time, the processor A reads the data on the data line.

If a parity error occurs when the parity check register 12 checks the parallel data output from the serial / parallel register 11, an error signal / ERR is transmitted through the second logic gate 9. Make it low.

When the line receive signal RXD output from the line receive 15 has an error pattern, an error is checked through the error detector 13, and the error signal / ERR is received through the second logic gate 9. Make it low.

When using a mode other than the above READ or WRITE, the data format of TXD (C) is sent when the MODE of FIG. 3 is used. This is similar to the write mode, and the address area is a desired mode area of the mode areas of FIG.

As described above, the present invention is composed of a small number of lines in the asynchronous serial communication method using a memory, not only economical effect by reducing the drive required for this, but also has the convenience of physical use. In addition, it provides the logical convenience of the parallel communication method that can use the counterpart memory as its own memory.

Claims (5)

Chip select signal (/ CS), read signal (/ RD), write signal (/ WR), address signal (ADDRESS), data signal (DATA), and CPU clock signal (CPUCLK) A processor A which selectively outputs and receives a reset signal / RESET, a weight signal / WAIT, an error signal / ERR, and the like; A mode register 1, an address register 2, a transmission data register 3 and a chip register signal / CS, a read signal / RD and a write signal / WR of the processor A ; Parallel / serial for transmitting the data format to the line drive 14 in synchronization with the clock signal CLK supplied from the mode register 1, the address register 2 and the transmission data register 3 from the outside. Register 10; A line drive 14 for transmitting the data format transmitted from the parallel / serial register 10 to the processor B; A parity generator 8 for generating parity bits falling into the lowest part of the data format; A wait register (4) for selectively receiving the input data value and providing a time delay and a reset signal (/ RESET) to the processor A, and outputting the value to the first counter 6; A first counter 6 that counts the CPU clock signal to produce a weight signal; A line receiver 15 for transmitting the data of the processor B to the processor A; A serial / parallel register 11 for dividing the data format input through the line receive 15 into a data portion and a parity bit portion, outputting data to processor A and parity bits to a parity check register 12; A parity check register (12) for detecting whether an error has occurred in the parity bit transmitted from the serial / parallel register (11) and outputting it to a second logic gate; An error pattern detector (13) for checking whether an error has occurred in the data format input through the line receive (15); A parity check register 12 and a second logic gate 9 for outputting an error signal / ERR to the processor A by logically calculating the value when an error signal is transmitted from the error pattern detector 13; A second counter 7 which receives the mode register 1, the signal output from the wait register 4 and the CPU clock signal CPUCLK and outputs the same to the first logic gate 5; And a first logic gate 5 for outputting a weight signal / WAIT to the processor A by performing a logic operation on the signal output from the first counter 6 and the second counter 7. Asynchronous serial communication transmitter / receiver between two processors using the other's memory. The method of claim 1, wherein when writing data from the processor A to the processor B, the chip select signal / CS and the write signal / WR are set to 'low' state in the processor A, and the address value is determined. When the transmit / receive data area is in the middle, the WRITE mode value is input to the mode register 1, while the address value on the address line is input to the address register 2, and the data value on the data line is After inputting to the transmission data register 3, when the CPU speed of the processor A is faster than the access timing, the number of CPU clock signals CPUCLK to be weighted is input to the wait register 4 as the wait register area, and the wait register ( When the reset value of 4) becomes the maximum value and is delayed by the value of the wait register 4 and input to the address register 2 and the transmission data register 3, the mode / adjustment in the parallel / serial register 10 is performed. An asynchronous serial communication transmission / reception device between two processors using a counterpart memory, characterized in that it is output as a signal (TXD) of a serial value line drive in a data format in the order of address, data, and parity bits. 3. The input data of the parallel / serial register (10) is simultaneously input to the parity generator (8), and the parity generator (8) generates a parity bit and inputs it to the parallel / serial register (10). Asynchronous serial communication between the two processors using the other party's memory, characterized in that for transmitting the data format output from the parallel / serial register 10 to a long distance to the processor B using a line drive 14 . The processor A of claim 1, wherein when the processor A intends to read the data of the processor B, the processor A sets the chip select signal / CS and the read signal / RD to a 'low' state, and an address value is transmitted / received. When the data area is in the middle, the read mode READ value is input to the mode register 1 and the address value on the address line is input to the address register 2 at the same time. The weight signal is independent of the wait register 4 value. In this case, the line receive signal RXD is inputted through the line receive 15, and the start bit is input to the second count 7 when the line receive signal RXD is in the normal state. When the line receive signal RXD is input to the serial / parallel register 11 and all the parallel data is output, the weight signal / WAIT is made from 'low' to 'high'. Lead to Asynchronous serial communication transmission / reception device between the two processors using a Li. The second logic gate according to claim 4, wherein when an error occurs in the parity bit when the parallel data output from the serial / parallel register 11 checks the parity bit through the parity check register 12. The error signal / ERR is set to 'low', and when the line receive signal output from the line receive 15 has an error pattern, the error is checked through the error detector 13, and the second logic gate 9) Asynchronous serial communication transmitting / receiving device between two processors using a counterpart memory characterized by detecting an error by making an error signal (/ ERR) low.