JPS60237562A - Control system for data transmission and reception - Google Patents

Abstract

PURPOSE:To reduce the load on a central processor and to transmit and receive data at a high speed by allowing a wiring logical device to take partial charge of control. CONSTITUTION:The data transmission/reception system consists of the 1st - the 4th address buses 102, 202, 302, and 402 for control, the 1st - the 4th data buses 101, 201, 301, and 401, a data transmitter receiver 1, a bus changeover switch 4, the central processor 2, and the wiring logical device 3. The wiring logical device 3 is equipped with a status information detecting circuit 31, control information generating circuit 32, data input circuit 33, data output circuit 34, control address generating circuit 35, interface circuit 36, and control circuit 37. The bus changeover switch 4 is switched to the side of the central processor 2 before data information is transferred from the data transmitter receiver 1 or to the data transmitter receiver 1, and the bus changeover switch 4 is switched to the side of the wiring logical device 3 during the transfer period.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission/reception control system, and in particular, a data transmission/reception control device, a bus changeover switch, a central processing unit,
The present invention relates to a data transmission/reception control method using a wired logic device.

In the conventional method, a control address bus for transferring internal register selection signals including read/write control signals,
A data transmitting/receiving device is connected to both a data bus used to transfer data to and from internal registers. This conventional data transmitter/receiver is manufactured by IHH commercially available integrated circuits, and is directly connected to the central processing unit via a control address bus. In this case, the speed at which data is transmitted and received between the data transmitting and receiving device and the outside cannot exceed a limit determined by the operating speed of the central processing unit. Therefore, while the data transmitting/receiving device is in operation, it becomes impossible to allocate the processing power of the central processing unit to other processing, or
The drawback was that the remaining power was much reduced. On the other hand, it has generally been difficult to apply direct memory access (DMA) control in place of the central processing unit because the control formats for the data transmitting and receiving devices would be inconsistent. In other words, in order to control a data transmitting/receiving device, it is necessary to control appropriate control address information according to the internal state, rather than simply transferring data along with read/write control signals as in direct memory access (DMA) control. The disadvantage is that in addition to the address bus, one of the internal registers must be fully selected and the appropriate data must be transferred via the selected register and the data bus.

An object of the present invention is to enable relatively low-speed operation before data transfer or after data transfer, and to control it by a central processing unit, while requiring high-speed operation during data transfer. The object of the present invention is to provide a data transmission/reception control system in which control is shared by logical devices, thereby reducing the burden on a central processing unit and enabling high-speed data transmission and reception.

The data transmission and reception control system according to the present invention includes first to fourth control address buses, first to fourth data buses, a data transmission and reception device, a bus changeover switch, a central processing unit,
It consists of a wired logic device. The first to fourth control address buses are buses for transferring internal register selection signals including read/write control signals. 1st
-The fourth data bus corresponds to the first to fourth control address buses, respectively, and is a bus for transferring data information. The data transmitter/receiver @ is connected to a first control address bus and a first data bus. The bus selection switch is connected to the data transmitting/receiving device via a first control address bus and a first data bus, and is connected to the central processing unit via a second control address bus and a second data bus. and is connected to the hardwired logic device via a third control address bus and a third data bus. The central processing unit is connected to the bus selector switch via a second control address bus and a second data bus, and is connected to the hardwired logic device via a fourth control address bus and a fourth data bus. It is connected. The hardwired logic device is connected to the bus selector switch via a third control address bus and a third data bus, and is connected to the central processing unit via a fourth control address bus and a fourth data bus. It is connected. Before data information is transferred from the data transmitting/receiving device or to the data transmitting/receiving device, the bus selector switch is switched to the central processing unit side, and the central processing unit performs an internal setting operation for the data transmitting/receiving device. During the transfer period, the bus changeover switch is switched to the wiring logic device side to control the transfer, and after the transfer period ends or a transfer error occurs, the bus changeover switch is switched to the central processing unit side again for operation.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a device implementing a data transmission/reception control method according to the present invention. This device has first to fourth control address buses 102, 202, 302, 402, and first to fourth data buses 101, 201, 301, 4.
01, and a data transmitting/receiving device 1. A central processing unit 2 and a wiring logic unit 3.

It is established from the bus changeover switch 4. The wiring logic device 3 includes a status information detection circuit 31, a control information generation circuit 32, a data input circuit 33, a data output circuit 34, a control address generation circuit 35, an interface circuit 36, and a control circuit 3T. This is what I did. A first control address bus 102 and a first data bus 101 are connected between the data transmitting/receiving device 1 and the bus changeover switch 4. A second control address bus 202 and a second data bus 201 are used to connect the central processing unit 2 and the bus changeover switch 4. A third control address bus 302 and a third data bus 301 connect the bus changeover switch 4 and the wiring logic device 3. A fourth control address bus 402 and a fourth data bus 401 connect the wiring logic device H3 and the central processing unit 2. When the bus selector switch 4 is switched to the central processing unit 2 side, the data transmitting/receiving device 1 is connected to the first control address bus 102 and the first data bus 101 . In addition, the central processing unit 2 is connected to the second control address bus 202 and the second data bus 2 (NTh). , the first control address bus 102, the first data bus 101, and the third control address bus 302 and the third data bus 3 from the data transmitting/receiving device 1.
A hardwired logic device 3 is connected via 01.

In the wiring logic device 3, the control circuit 37Fi first has A,
It has four states, B, C, and D, and has the role of determining the position of the bus changeover switch 4 corresponding to each state. The control circuit 37 secondly connects the circuits to be connected to the data bus 301 via the interface circuit 36 to the status information detection circuit 31 . Control information generation circuit 32. Data input circuit 33.
Data output circuit 34. One of the control address generation circuits 35 is selected and activated. Thirdly, the control circuit 37 causes the control address generation circuit 35 to generate appropriate control address information.

Next, the operation of one embodiment of the data transmission/reception control system shown in FIG. 1 will be described, taking the case of data reception as an example.

In the initial state, the control circuit 37 is set to state A. At this time, the bus selector switch 4 is switched to the central processing unit 2 side, and the internal registers of the data transmitting/receiving device 1 are set by the central processing unit 2.

Next, when the central processing unit 2 shifts the state of the control circuit 31 to state B, the control circuit 31 changes from state A to state B.
As T changes state, the bus selector switch 4F
When switched to the wiring logic device 3 side, the data transmitting/receiving device 1 operates under the control of the wiring logic device 3. In state B, the control address generation circuit 35 generates all control address information for requesting status information. This information is passed to the interface circuit 36 and the third control address bus 30.
2, the bus selector switch 4, and the first control address bus 102 to the data transmitting/receiving device 1.

Conversely, from the data transmitting/receiving device 1 to the first data bus 101
Status information is sent to the third data bus 301.
and an interface circuit 36 to the status information detection circuit 31. Status information detection circuit 3
When the status information indicating the receivable state is detected, the output of the status information detection circuit 31 is applied to the control circuit 37, and the control circuit 3T shifts to state C.

In state C, the control address generation circuit 35 generates control address information for requesting received data. At this time, the received data sent from the data transmitting/receiving device 1 is applied to the data input circuit 33. After this, the state of the control circuit 37 may be in state C or may again shift to state B, and the operation after the status detection described above? :Repeat. If the status information detection circuit 31 detects status information indicating # network data receivable state while the control circuit 3T is set to state B, the state of the control circuit 3T shifts to state C. In this state, after the last data is applied to the data input circuit 33 by the control circuit 3T, the state shifts to the state of the control circuit 37. In this state, the control information generation circuit 32 and the control address generation circuit 35 generate control address information and other control information necessary for processing after receiving the final data.

This information is transmitted to the first control address bus 102 and the first control address bus 102.
is applied to the data transmitting/receiving circuit 1 via the data bus 101. Thereafter, the state of the control circuit 37 returns to the PH state AK, and the bus changeover switch is being turned on.

Switching to the central processing unit 2 side, the data transmitting and receiving device 1 operates under the control of the central processing unit 2 .

In the above explanation, the case of receiving data was explained, but in the case of transmitting data, the data input circuit 3
A data output circuit 34 is used instead of 3. but,
There is essentially no difference except that the state transition method of the control circuit 37 is changed as necessary. Furthermore, even when data is received, it goes without saying that the state transition method of the control circuit 37 generally differs depending on the content of each system or the selection method of the data transmitting/receiving device 1 to which it is applied.

As explained above, according to the data transmission/reception control method according to the present invention, the processing content tends to become complicated during the period when relatively low-speed processing is possible before data is transferred or after data is transferred. Control is performed from the central processing unit, and during the high-speed processing period when data is transferred, even if the processing content is simple, high-speed processing is essential, so control can be performed from the wired logic unit. Therefore, according to the present invention, data transmission and reception can be controlled at high speed, and the burden on the central processing unit can be significantly reduced.

Furthermore, the wiring logic device in the data transmission/reception control method according to the present invention has the advantage that it can be constructed with a relatively small-scale circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a device implementing a data transmission/reception control method according to the present invention. 1...Data transmitting/receiving device 2...-Central processing unit 3, φ, Wiring logic device 4, 11@bus changeover switch 31...Status information detection circuit 32...Control information generation circuit 33...Data Input circuit 34...Data output circuit 35...Control address generation circuit 36...Interface circuit 3T...Control circuit 102, 202, 302, 402--...Control address bus

Claims (1)

[Claims] first to fourth control address buses for transferring internal register selection signals including read/write control signals;
first to fourth data buses for transferring data information corresponding to the first to fourth control address buses, respectively; and the first control address bus and the first data bus. a connected data transmitting/receiving device, a bus changeover switch connected to the data transmitting/receiving device via the first control address bus and the first data bus, and the second control address bus and the first data bus. a central processing unit connected to the bus changeover switch via a second data bus; and a central processing unit connected to the bus changeover switch via the third control address bus and the third data bus; a hardwired logic device connected to the central processing unit via a fourth control address bus and the fourth data bus; Before the data is transferred to the data transmitting/receiving device field, the bus selector switch is switched to the central processing unit side, and an internal setting operation is performed from the central processing unit to the data transmitting/receiving device. The bus selection switch 1kI! The transfer operation is controlled by switching to the fI writing logic device, and after the transfer period ends or a transfer error occurs, the bus changeover switch is switched to the central processing unit side again. A data transmission/reception control method characterized by being configured to switch.