JPH034942B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer control method in a data processing system, and in particular, to prevent overruns from occurring in data transfer between a file adapter and an input/output control device. This invention relates to a data transfer control method for preventing erroneous processing when

[Conventional technology]

In some data processing systems, main memory and
A buffer mechanism called a file adapter is provided in order to smoothly transfer data to and from the 0 control device. FIG. 2 shows the outline thereof, and 1 is a main memory, 2 is a file adapter, and 3 is an I/0 control device.

First, when transferring a certain amount of data from main memory 1 to I/0 control device 3, from main memory 1 to file adapter 2, up to
Transfer data up to the capacity of File Adapter 2.
As shown in FIG. 3, the I/0 control device 3 sends a request signal REQ requesting data to the file adapter 2 for each piece of data, and in response, the file adapter 2 sends a request signal REQ to the I/0 control device 3. Adapter 2 has data DATA and acknowledge signal ACK
is sent to the I/0 control device 3, and the I/0 control device 3
transfers data by repeating the operation of fetching data DATA a predetermined number of times when it detects an acknowledge signal ACK.

Next, when transferring data from the I/0 control device 3 to the main memory 1, from the I/0 control device 3 to the file adapter 2, up to
data is transferred up to the capacity of , and further data is transferred from the file adapter 2 to the main memory 1. Note that when transferring data from the I/0 control device 3 to the file adapter 2, as shown in FIG.
For each piece of data, the I/0 control device 3 sends the data DATA and a request signal REQ requesting reception to the file adapter 2. When the file adapter 2 detects this request signal REQ, it takes in the data DATA and at the same time sends an acknowledgment. This is done by repeating the operation of returning the signal a predetermined number of data.

In such a conventional method, the maximum number of request signals REQ that can be transmitted by the I/0 control device is defined by the file adapter 2 by matching the number of transmitted request signals REQ and the number of acknowledgment signals ACK. ing. The file adapter 2 has an internal buffer with a capacity equal to the above-mentioned maximum number, so that it can receive all the data transmitted from the I/0 control device 3.

[Problem that the invention seeks to solve]

In the conventional method, the file adapter requires a buffer with a capacity equal to the maximum allowable number of request signals REQ, so the buffer becomes large and the request signal that the I/O control device can send is
There was a problem that the number of REQs was limited.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention does not make the buffer capacity of the file adapter equal to the maximum allowable number of request signals imposed on the I/0 control device, and the I/0 control device This allows request signals to be sent in excess of the buffer capacity of .

However, this may result in data transfer overrun at the file adapter.
That is, when the file adapter receives a request signal from the I/0 control device, the data to be sent is not yet prepared in the buffer of the file adapter, or when the file adapter receives the request signal and data, There may be cases where there is no space in the adapter's buffer to store the data, and the file adapter will not respond with an acknowledge signal to the I/O control device, resulting in loss of synchronization, or will only respond with an acknowledge signal. However, the problem arises that the data is not transferred correctly, and the process ends with an error, which takes time to recover.

Therefore, in the present invention, an overrun indicating flip-flop is provided, and when a request signal is received when an overrun occurs, that is, when there is no data to be sent to the buffer of the file adapter,
This overrun display flip-flop is set to ON, and its output is used to control, for example, sending pseudo data of "0" in the case of a data transmission request, and to ignore the received data in the case of a data reception request. The problem is solved by sending a signal.

[Action of the invention]

According to the present invention, if there is no data in the buffer at the time when a request signal requesting data transmission is sent from the I/0 control device to the file adapter, and an overrun occurs, an overrun display flip-flop is activated. turns ON, and normal pseudo data with parity is sent together with an acknowledge signal.

Also, if there is no free space in the buffer and an overrun occurs when the I/O control device sends a request signal requesting data reception to the file adapter and data is sent, the overrun indication flip-flop turns on and the data is not received. An acknowledge signal is sent without ignoring the data and storing it in the buffer.

Therefore, the I/0 control device recognizes the number of transmitted request signals and the number of received acknowledgment signals corresponding thereto as normal, and can proceed with data transfer to the end. After the data transfer is completed, the firmware checks the state of the overrun display flip-flop.
If it is “ON”, take appropriate measures such as retransferring data.

〔Example〕

Hereinafter, details of the present invention will be explained based on examples.

FIG. 1 is a circuit diagram of a file adapter constructed as one embodiment of the present invention. In the figure,
1 is main memory, 2 is file adapter, 3 is I/
0 is a control device, 4 is a buffer, 5 is an overrun display FF, 6 is an overrun state detection circuit, 7 is an acknowledge signal generation circuit, 8 to 11 are AND
12 is an inverter, and 13 to 16 are drivers/receivers. Also, ACK is an acknowledgment, REQ is a request, DATA is data,
Read represents data transfer from the I/0 control device to the file adapter, Write represents data transfer from the file adapter to the I/0 control device, Full represents the state where there is no space in the buffer, and Empty represents the state where there is no data in the buffer. It's a signal.

Buffer 4 includes main memory 1 and I/0 control device 3
It is used to transport data both ways.

Overrun indicator FF5 is set to ON when both the output of overrun state detection circuit 6 and request signal REQ are "1". In other words, the overrun state detection circuit 6 recognizes an overrun and outputs "1" when either the buffer is Full with no empty space during Read or the buffer is Empty with no data during Write.
Output. Here, when REQ is input from the I/0 control device 3 via the driver/receiver 14, the output of the AND gate 8 becomes "1", and the overrun indicator FF5 is inverted from OFF to ON.
Once overrun display FF5 is turned ON, it remains ON until the micro is turned OFF.

When the acknowledge signal generation circuit 7 receives the REQ, it unconditionally generates an ACK and sends it back to the I/0 control device 3 via the driver/receiver 13.

AND gate 9 operates when REQ is "1" and overrun display FF5 is OFF, that is, when there is no overrun and the output of inverter 12 is "1".
When REQ is input, it outputs "1" to enable the buffer 4. When the output of the inverter 12 is "1", the AND gates 10 and 11 are also open, and the driver/receiver 1
DATA from the I/0 control device 3 is stored in the buffer 4 via AND gate 10 and DATA taken out from the buffer 4 via AND gate 11 and driver/receiver 16.
An operation is performed to transmit the information to the I/0 control device 3.

On the other hand, when an overrun occurs and the overrun display FF is ON, the output of the inverter 12 becomes "0", so the AND gates 9, 10, and 11 become inoperable, and data input to the buffer 4 is disabled. No output operation is performed. Therefore
During a write operation, if an overrun occurs, as illustrated in FIG.
is sent as pseudo data to the I/0 control device 3 along with ACK, and the next data transfer is performed. Figure 5 shows data “A” from the file adapter,
This is an example in which data "B" could not be prepared in the buffer when transferring "B" and "C", resulting in an overrun.

Similarly, during a Read operation, as illustrated in FIG. 6, if an overrun occurs, the received DATA "B" is ignored by the file adapter, an ACK is sent, and the next data transfer is performed. Figure 6 shows that when the file adapter receives data “X”, “Y”, and “Z”, data “Y”
This is an example of an overrun because there was no space in the buffer.

The pseudo data DATA "0" is data in which all bit values are "0" and is easily generated since the output of the AND gate 11 at the time of overrun is "0". However, other suitable pseudo data can be used. Further, a parity circuit (not shown) adds parity to the pseudo data in the same way as normal data and transmits the data.

〔Effect of the invention〕

As described above, according to the present invention, the buffer capacity of the file adapter and the maximum allowable number of request signals in the I/0 control device can be set separately, thereby making the buffer capacity of the file adapter relatively small. be able to.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of one embodiment of the present invention, Fig. 2 is a schematic diagram of a system using a file adapter, and Fig. 3 is a control when transferring data from a conventional file adapter to an I/0 control device. A diagram explaining the procedure, Figure 4 is a diagram explaining the control procedure when transferring data from a conventional I/0 control device to a file adapter, and Figures 5 and 6 are books corresponding to Figures 3 and 4, respectively. FIG. 3 is an explanatory diagram of a control procedure according to an embodiment of the invention. In the figure, 1 is the main memory, 2 is the file adapter,
3 is an I/0 control device, 4 is a buffer, 5 is an overrun display flip-flop, 6 is an overrun state detection circuit, 7 is an acknowledge signal generation circuit,
REQ indicates a request signal, ACK indicates an acknowledge signal, and DATA indicates data.

Claims (1)

[Claims] 1. In a data processing system equipped with a file adapter having a buffer function between the main memory and an I/O control device, the file adapter has a buffer and an overrun indication flip-flop, and the I/O When transferring data to the 0 control device, the I/0 control device sends a request signal, and in response, the file adapter sends an acknowledge signal and the data in the buffer. If not, the overrun indicating flip-flop is set to ON to transmit pseudo data, and when data is to be transferred from the I/0 controller to the file adapter, the I/0 controller transmits a request signal and data. , the file adapter transmits an acknowledge signal in response to the request signal, and stores the received data in the buffer, and if there is no free space in the buffer, it sets the overrun indication flip-flop to ON and stores the received data. This data transfer control method is characterized in that even if an overrun occurs, the data transfer is executed to the end in the same way as normal.