JP2752456B2 - Channel device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] At least, synchronous transfer can be performed with a lower-level device, and a transfer request signal can be transmitted without waiting for a device that issues a transfer request to receive a transfer response signal. A data transfer termination instruction for a channel device configured so that a device that issues a transfer response can determine the number of data to be received or transmitted by itself when the number of data to be received is received. The purpose of the present invention is to provide a data buffer that can transmit a signal and correctly return a data transfer response signal even if a delay occurs in data transfer. A request / response number difference stack that holds the difference from the number of signals sent is provided, and data that gives the timing for sending a data transfer end instruction signal is also provided. It is configured to include an end instruction stack to equity.

[Industrial applications]

According to the present invention, a transfer request signal can be transmitted without receiving a transfer response signal from a channel device, in particular, at least a synchronous transfer with a lower device side, and the transfer requesting device can receive the transfer response signal. The present invention relates to a channel device configured so that a device that issues a response can determine the number of data to be received or transmitted.

Since the length of the data line has become so long that it has become necessary to make the transmission time during signal transmission a problem, the synchronous transfer method is adopted, but the response corresponding to the transfer request signal issued by itself is used. An interface is employed in which a transfer request signal is transmitted one after another without waiting for reception of a signal. It is also desirable to determine the number of data to be received by itself and to transmit a data transfer end instruction signal at an appropriate time when the number of data is received.

[Conventional technology]

An interface is used that sends out a transfer request signal one after another without waiting for receiving a response signal corresponding to the transfer request signal issued by itself.

However, in the conventional case, there is no management means for managing the difference between the number of received transfer request signals and the number of transmitted transfer response signals.

For some reason, for example, an undesired delay may occur in data transfer with a higher-level device, and a transfer response signal may not be returned as desired immediately after receiving a transfer request from a lower-level device. For this reason, it may be difficult to find the timing at which the data transfer end instruction is issued.

[Problems to be solved by the invention]

In the conventional case, since the management means is not provided, there is a possibility that a transfer response signal to be returned cannot be returned correctly. Further, as described above, the timing of returning the transfer response signal may be undesirably delayed, and it is difficult to find the timing of issuing the data transfer end instruction. For this reason, when transferring data from a lower device to a higher device, a number of data transfer request signals corresponding to the number of data to be received by itself (it may be considered that data is transferred together with this signal) are received. If the data transfer end instruction signal is transmitted at the point in time, the data transfer end instruction signal may be transmitted first in a state where the transfer response signal to be returned cannot be returned as described above.

An object of the present invention is to enable a data transfer end instruction signal to be sent when the number of data to be received is received, and to correctly return a data transfer response signal even if a delay occurs in data transfer. It is an object.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. Reference numeral 1 in the figure denotes a channel processor (hereinafter also referred to as a channel device), 2
Denotes a higher-level device, which is represented by a main storage device (MS) in the case shown, and 3 denotes a lower-level device, which is represented by an input / output device (IO) in the case shown. ing.

4 is a data buffer. Further, reference numeral 5 denotes a request / response number difference stack provided in the present invention, which corresponds to, for example, successive transmission of a transfer request signal from the lower device 3 and accumulation of data in the data buffer 4 as shown in the figure. Then, the channel device 1 sequentially returns a transfer response signal notifying that the data has been received. However, the number of received transfer request signals during this time and the transfer response signal are transmitted. The difference from the number sent is kept.

Reference numeral 6 denotes an end instruction stack provided in the present invention, which is suitable for the number of data to be received even if the return timing of the transfer response signal is delayed for some reason as described above. It is possible to send a data transfer end instruction signal when returning a number of transfer response signals.

(Operation)

Now, consider transferring data from the lower-level device 3 to the higher-level device 2. In this case, the lower order device 3 sends out data in response to the transfer request signal, and sends out the transfer request signal (along with the data) one after another without waiting for the reception of the transfer response from the channel device 1.

The transmitted data is temporarily stored in the data buffer 4 and then transferred to the host device 2. The channel device 1 responds to the reception of the individual transfer request signals by a transfer response. Send back signal.

The request / response number difference stack 5 holds a value corresponding to the difference between the number of transfer request signals received and the number of transfer response signals transmitted, so that the number of transfer response signals to be returned can be managed. I have.

On the other hand, when the channel device 1 knows the number of data to be received by itself and receives the transfer request signals of the number corresponding to the data number N, the contents of the request / response number difference stack 5 at this time point r is transferred to the end instruction stack 6. The value r indicated by the content should be returned after the time to return the number of transfer response signals corresponding to the number N when the number of transfer request signals corresponding to the number N of data is received. This shows the number of transfer response signals. From this, the channel device 1 increments the content r of the end instruction stack 6 by one each time the transfer response signal is returned thereafter, so that the data transfer end instruction signal can be transmitted.

〔Example〕

FIG. 2 shows an embodiment of the present invention. Symbol 1 in the figure
Is the channel device (channel processor), 4 is the data
A buffer, 5 is a request / response number difference stack, 6 is a termination instruction stack, 7, 8 are a data bus, 9 is a bus control circuit, and 10 is a response availability determination unit. 11 is a transfer request signal receiving circuit, 12 is a transfer response signal sending circuit, and 13 is a data transfer end instruction signal sending circuit.

The contents of the request / response number difference stack 5 are incremented by one in response to the detection of the reception by the transfer request signal receiving circuit 11, and decremented by one in response to the transmission by the transfer response signal transmitting circuit 12.
The response availability determination unit 10 determines whether to transmit a transfer response signal in consideration of the number of data currently stored in the data buffer 4 and the contents (value) of the request / response number difference stack 5. . If it is to be sent, a sending instruction is sent to the transfer response signal sending circuit 12.

Also, the response availability determination unit 10 knows the number N of data to be received by the channel device 1 and, when receiving the transfer request signal of the number N, receives the request / request at that time.
End contents stack 6 of response number difference stack 5
Will be transcribed to.

Thereafter, the content of the end instruction stack 6 is decremented by 1 in response to the transmission by the transfer response signal transmission circuit 12, and when the content becomes, for example, "1", the data transmission end instruction signal transmission circuit 13 And issues a termination instruction transmission instruction.

If a transfer response signal is not sent when sending a data transfer end instruction signal as in the case of a known IPI interface, the contents of the request / response number difference stack 5 shown in FIG. Is sent out so as to be decremented by one.

FIG. 3 is a time chart when the transmission of the second transfer response signal is delayed, and FIG. 4 is a time chart when the transmission of the third transfer response signal is delayed.

3 and 4, assuming that the number of data to be received by the channel device 1 is N = 3, when three transfer request signals are received, the stack 5
Is transferred to the stack 6. In the case shown in FIG. 3, since the transmission of the second transfer response signal is delayed, the value “3” is transferred to the stack 6. Further, in the case of FIG. 4, since the transmission of the third transfer response signal is delayed, the value of “2” is stored in the stack 6.
Is posted.

Thereafter, the contents of the stack 6 are decremented by one in response to the transmission of the transfer response signal. Then, when the content of the stack 6 becomes the value "1", an operation is activated to send a data transfer end instruction signal.

As a result, when the number of transfer response signals corresponding to the number of data to be received N = 3 is transmitted, a data transfer end instruction signal is immediately issued, so to speak, the transmission of the subsequent transfer request signal is terminated.

In the conventional case, since the end instruction stack 6 does not exist, if a data transfer end instruction signal is sent immediately upon receiving a transfer request signal corresponding to N = 3, for example, a predetermined number of transfer The data transfer end instruction signal is sent before the response signal is sent.

〔The invention's effect〕

As described above, according to the present invention, it is possible to send a data transfer end instruction signal at a correct timing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are time charts, respectively. In the figure, 1 is a channel device (channel processor), 2 is an upper device (main storage device), 3 is a lower device (input / output device), 4 is a data buffer, 5 is a request / response number difference stack, and 6 is a Indicates an end instruction stack.

Claims (1)

(57) [Claims] A channel device (1) provided between a higher-level device (2) and a lower-level device (3) and having a data buffer (4) for data transfer, at least the lower-level device. (3) Synchronous transfer can be performed with the device, and the number of transfer request signals that can be transmitted by the device that issues the transfer request prior to receipt of the transfer response signal can be determined in advance. In the channel device (1), the transmitting device determines the number of data to be received or transmitted and can transmit a data transfer end instruction signal in response to the predetermined number of receptions or transmissions. A request / response number difference stack (5) is provided for holding the difference between the number of received transfer request signals and the number of transmitted transfer response signals, and a number corresponding to the number of data to be received by itself. When the transfer request signal is received, the contents of the request / response number difference stack (5) are transcribed, and the transfer request signal corresponding to the number of data to be received by the self is determined by the self. A channel device, comprising: a termination instruction stack (6) for transmitting the data transfer termination instruction signal when the transmission response signal corresponding to the number is transmitted.