JPH0136740B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data bus control system, in which data is transferred between computers or equivalent devices connected to a common bus consisting of a plurality of signal lines, and in particular, all computers use the same method. The present invention relates to a data bus control system that monopolizes a common bus and allows high-speed data transfer through simple arrangements.

An example of data transfer in a conventional data bus control system will be explained with reference to FIG. In Figure 1, 1
is a common bus, A1, B1, and C1 are computers that transfer data via the common bus 1, and D1 is a bus control computer. Common bus 1
is composed of a plurality of data lines and a plurality of control lines for transferring data between computers connected to it. When transmission information is generated, computers A1, B1, and C1 monopolize common bus 1 at an appropriate time with permission from bus control computer D1, attach destination addresses to the data, and send data on common bus 1 in bytes or words. Send to data line. Further, the computers A1, B1, and C1 constantly monitor the data on the common bus 1, and if the data is not addressed to their own station, they ignore it, and if it is addressed to their own station, they take it into their internal memory.

Bus control computer D1 includes computers A1, B1, C
It may also have the same operations as 1, but in addition, it also controls the entire system to determine which computer is given the right to exclusively use the bus. There are various ways to grant bus exclusive rights; for example, the following methods are available. That is, the bus control computer sends special information defined as a polling message to one computer in the system. Each computer ignores the polling message if it is not addressed to its own station, but if it is addressed to its own station, it can obtain bus exclusive rights at that point. If a computer that has obtained bus exclusive rights has transmitted data at that time, it can send the data to the common bus with an appropriate destination address attached. When the computer has finished sending the data,
Notify the control computer that bus exclusive rights will be relinquished in some way. Furthermore, when the computer receives the polling message, if there is no data to be sent, it will not transmit data and immediately relinquish its exclusive right to the bus.

When the bus control computer learns that the computer that sent the polling message has given up exclusive rights to the bus, it then sends the polling message to a different computer. In this manner, a plurality of computers transfer data via the common bus according to instructions from the bus control computer.

Another conventional method is that instead of each bus control computer sequentially issuing a polling message, the computer that has all the data to send interrupts the bus control computer using an appropriate signal line within the common bus. , there are those that solicit something equivalent to polling messages.

In this way, when a plurality of computers transfer data via a common bus, a special computer usually exists in order to give the computer exclusive rights to the bus.

However, according to each of the above conventional systems, since there is only one bus control computer with a special function in the system, if the bus control computer fails, the entire system will fail. Another disadvantage is that the procedure for granting bus exclusive rights to each computer is troublesome, resulting in wasted time.

The present invention eliminates the above-mentioned drawbacks, and there is no special computer that controls the exclusive right of the common bus, and all computers can monopolize the common bus in a simple and same way. It is an object of the present invention to provide a data bus control method that enables mutual data transfer and allows a high common bus utilization rate to be obtained by allowing only valid data to flow through the common bus.

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 2 and subsequent figures. FIG. 2 shows a block system diagram of an embodiment of the data bus control system according to the present invention.

In FIG. 2, 2 is a common bus according to the gist of the present invention, and 3 is a clock generator. A2, B
2, C2, and D2 are computers that transfer data via a common bus.

Common bus 2 has two different clock lines, one dedicated bus line, one address tag line, one response tag line, one data tag line, and one parity check line. Consists of nine data lines including:
Clock generator 3 drives two different clock lines among these nine data lines. Next, the signal lines of the common bus 2 will be explained.

The first clock line is for synchronizing the exclusive operation of the common bus 2, and is for synchronizing the bus exclusive operation of the common bus 2.
Driven by. All computers perform operations related to bus exclusive use in synchronization with this clock.

The second clock line is a clock obtained by dividing the frequency of the first clock line by N, and is driven by the clock generator 3 to provide timing so that each computer can monopolize the common bus 2 without contradiction. The frequency division ratio N can be changed depending on the system. Here, if the number of computers connected to the common bus 2 is M, then M≦N must be satisfied.

The dedicated bus line is constantly monitored by each computer, and for example, if logic L is significant, when the dedicated bus line is significant "L", it means that another computer is already monopolizing the common bus 2. You cannot get exclusive rights. When this bus exclusive line is “H”,
This dedicated bus line can be driven to a significant "L" level at a timing specific to each computer determined by the first clock and the second clock. The computer that drives this bus exclusive line to "L" gains exclusive rights to the common bus 2, and can transmit data by the method described later.

The address tag line is driven to "L" by the computer that exclusively uses the common bus 2. At the same time, the destination address is sent to nine data lines.

The data tag line is driven to "L" after the destination address is sent by the computer that exclusively uses the common bus 2. Note that transmission data is sent out at the same time.

The response tag line is driven by the receiving computer, and when the transmitting computer finishes sending data, the response tag is driven to "L" and at the same time, response information is sent to the data line.

The data line is a line for transferring address, data, and response information, and includes one line for parity checking.

The bus exclusive line is connected to each computer by a circuit configuration such as an open collector, and when any one computer outputs a significant "L" signal, the signal line becomes "L".

Next, how a plurality of computers monopolize a common bus and transfer data without a bus control computer will be explained with reference to FIG. FIG. 3 is an example of a time chart for explaining data transfer according to the method of the present invention.

In FIG. 3, the dash-dotted line indicates that the clock generation circuit 3
The solid line is a signal driven by a computer that transmits data, and the two-dot chain line is a signal driven by a computer that receives data. AD is the destination address, DT is the transmission data,
R1 indicates response information 1.

Here, a unique address i is assigned to a computer connected to the common bus 2 under the following conditions.

0≦i≦M-1 Here, as mentioned above, M is the number of computers connected to the common bus 2, and for the frequency division ratio N of the first clock and the second clock, M≦N. There is a relationship.

For example, the bus exclusive line indicating that the computer has exclusive use of the common bus 2 can be driven to "L" at the following timing. That is, the computer at address i is
The first clock signal counts from the rising edge of the second clock signal.
The bus exclusive line can be set to "L" in synchronization with the i-th rise of the clock signal. If one of the computers sets the bus dedicated line to “L”,
No other computer can obtain the dedicated bus line until this returns to "H". That is, since all the computers have different addresses, the timing at which the dedicated bus line is set to "L" is different.
Further, while the bus dedicated line is at "L", other computers are in a standby state, so that the common bus 2 will not be monopolized by two computers at the same time.

In the example shown in FIG. 3, the computer with address i=3 monopolizes common bus 2,
Since the frequency division ratio of the first clock signal and the second clock signal is 4, the number of computers connected to the common bus 2 is limited to four or less.

The computer that has set the bus exclusive line to "L" first drives the address tag line to "L" and at the same time sends the destination address AD to the data line, then sets the data tag line to "L" and transmits. Data DT is also sent to the data line.

On the other hand, the receiving computer detects its own address on the data line in synchronization with the address tag line, and then
While the data tag line is at a significant "L" level, the data on the data line is taken into the internal memory. After completion of reception, the result of the parity check of the received data is sent out on the data line in synchronization with the response tag line.

If the response result is normal, the sending computer stops driving the exclusive bus line and relinquishes the exclusive right to the bus. The bus exclusive line becomes "H", and from this point on, other computers are also given the opportunity to exclusively use the bus. If the response result is an error, you can continue to retransmit with the bus dedicated line set to "L", or you can relinquish the bus exclusive right and notify the software that an error has occurred, and then The handling may be entrusted to software.

In this way, according to the above method, multiple buses can share the common bus 2 and transfer data to each other, and there is no need for a bus control computer that performs complicated bus exclusive control within the system. In addition, bus-specific control operations can be performed using a computer with additional simple functions. Therefore,
Failure of one computer does not lead to failure of the entire system, and bus exclusive control is performed by simple agreement, so there is no wasted time such as polling messages, and high transfer efficiency is achieved.

In the above embodiment, when the sending computer obtains bus exclusive rights, it unilaterally sends the address and data regardless of the state of the receiving computer.
There is a possibility that the following problems may occur. That is, assume that computer A2 now sends data to computer B2, and computer B2 returns a response indicating that it has been successfully received. Computer A2 relinquishes the exclusive right to the bus, but next time computer C2 acquires the exclusive right to the bus and sends data to computer B2.
If the computer has not yet finished processing the data received from the computer A2, the data from the computer C2 cannot be accepted and will be discarded. Calculator C
2 performs retransmission, so the data will be transferred eventually, but it is undesirable from the standpoint of bus utilization to transfer such useless data, and this becomes a problem especially when the data length is long.

In order to solve this problem, in other embodiments shown below, another function is added to each computer. That is, after the sending computer sends out an address in synchronization with the address tag line, it does not immediately proceed to data transfer, but waits for a response from the receiving computer. Also, the receiving computer checks whether its own station is in a state where it can accept data.
Immediately send a response to the data line in synchronization with the response tag signal. Based on this response, the sending computer can select whether to send the data or not to send the data and give up the exclusive right to the bus.

FIG. 4 is an example of a time chart for explaining data transfer using the above method. In the same figure, R
2 is response information 2 indicating whether reception is possible;
Other symbols and their meanings are the same as those in FIG.

After the transmitting computer transmits the destination address AD, the receiving computer immediately responds by transmitting on the data line in synchronization with the response tag signal whether or not its own station is in a state in which it can accept data. When the sending computer sees this response and determines that the data can be received, it sets the data tag line to "L" and sends the data to the data line. If the receiving side determines that it cannot receive data, it immediately abandons the exclusive right to the bus, as shown by the dotted line in FIG. As for the next transmission timing, the same operation may be performed again at a time when the receiving side becomes able to receive data again. Since the bus exclusive right is released during this time, data can be transferred between different computers using the common bus.

In this way, by first checking the status of the receiving computer and starting the data transfer before actual data transfer, it is possible to eliminate unnecessary data transfer and increase the utilization rate of the common bus 2.

[Brief explanation of drawings]

FIG. 1 is a block system diagram for explaining a conventional data transfer system, FIG. 2 is a block system diagram of an embodiment of the data bus control system according to the present invention, and FIG.
The figure is an example of a time chart for explaining data transfer using the data bus control method according to the present invention.
FIG. 4 is an example of a time chart for explaining data transfer according to another embodiment of the data bus control system according to the present invention. 2...Common bus, 3...Clock generation circuit, A
2, B2, C2...computer, D2...bus control computer.

Claims (1)

[Claims] 1. In a data bus control system that includes a plurality of computers and a common bus that connects them, and is controlled to transfer data between arbitrary computers via the common bus, there is a method for starting bus exclusive use. A clock generation circuit for generating a first clock signal for providing timing and a second clock signal for determining a reference starting point of the first clock signal is provided at one location in the system, and the common bus is At least two different clock lines for transmitting the first and second clock signals, a data line for transferring multiple data, and one line for indicating that the computer has acquired exclusive rights to the common bus. When a transmission request occurs, each computer connected to the common bus is equipped with a dedicated bus line, and if the common bus is not dedicated, the computers connected to the common bus are When a predetermined number of separate counts is counted by the first clock signal, the bus exclusive line is significantly driven, the destination computer address information and the transmission data are output to the data line, and data of an arbitrary data length is output. A data bus control system characterized by having a function of restoring the dedicated bus line when data transfer is completed. 2. In a data bus control system that is equipped with a plurality of computers and a common bus that connects them, and is controlled to transfer data between the computers via the common bus, the first method is to provide the timing for starting bus exclusive use. A clock generation circuit that generates a clock signal and a second clock signal that determines the reference starting point of the first clock signal is provided at one location in the system, and the common bus is connected to at least the first and second clock signals. Two different clock lines for sending out clock signals, a data line for transferring multiple data, a dedicated bus line that indicates that the computer has acquired exclusive rights to the common bus, and a line on the data line. An address tag line indicating that a destination address is being sent to the above data line, a data tag line indicating that transmission data is being sent on the above data line, and a response indicating that response information is being sent on the above data line. When a transmission request is generated, each computer connected to the common bus is equipped with a tag line, and if the common bus is not exclusively used, the computers connected to the common bus receive a signal that is predetermined for each computer based on the change point of the second clock signal. At the time when the separate count numbers are counted by the first clock signal, the bus exclusive line is activated to make the address tag line significant, and at the same time, the destination computer address information is output to the data line, and then the reception is performed. If the receiving side receives the response information from the side computer and is able to accept the data, it subsequently makes the data tag line significant and at the same time outputs the transmission data to the data line, and when the data transfer of the desired data length is completed, the data is transferred to the bus. A data bus control system characterized by having a function to restore the bus dedicated line to its original state if the receiving side cannot accept data.