JPH03102448A - Channel device - Google Patents

Abstract

PURPOSE:To correctly send back a data transfer answer signal despite a delay caused to the transfer of data by holding the difference between the number of received transfer request signals and the number of transmitted transfer answer signals and also holding the data secures the transmission timing of a data transfer and instruction signal. CONSTITUTION:A channel device 1 receives the transfer request signals in number corresponding to the number N of data and transcribes the contents (r) of a request-answer number difference stack 5 obtained at a relevant time point to an end instruction stack 6. The value of the contents (r) shows the number of transfer answer signals to be returned for return the number of transfer answer signals equivalent to the number N of data obtained when the number of transfer request signals corresponding to the number N of data. Therefore the device 1 hereafter gives -1 to the contents (r) of the stack 6 every time a transfer answer signal is returned and transmits a data transfer and instruction signal. As a result, the data transfer answer signal is correctly returned despite a delay caused to the transfer of data.

Description

[Detailed Description of the Invention] [Summary] At least. A channel device that performs one synchronous transfer with the lower device side, can send a transfer request signal without waiting for the reception of a transfer response signal, and can determine the number of data that it should receive. The purpose is to be able to send a data transfer end instruction signal when the desired number of data is received, and to be able to correctly return a data transfer response signal even if there is a delay in data transfer. In addition to providing Provides a request/response number difference stack that holds the difference between the number of received data that received a transfer request signal and the number of sent data that sent a transfer response signal, and also holds data that provides a timing for sending a data transfer end instruction signal. Prepare a termination instruction stack and be on guard.

(Industrial Application Field) The present invention is capable of performing synchronous transfer between a channel device, particularly at least with a lower-level device, and transmitting a transfer request signal without waiting for reception of a transfer response signal. The present invention relates to a channel device that can determine the number of data to be received.

Synchronous transfer method 2 was adopted because the length of the data line became large and it became necessary to consider the transmission time during signal transmission, but in order to respond to the transfer request signal issued by the self. An interface is employed in which transfer request signals are sent out one after another without waiting for response-3 to be received.

Also, determine the number of data that it should receive. It is desirable to send a data transfer end instruction signal as soon as the relevant number of data is received.

[Conventional technology]

An interface is employed that sends out transfer request signals one after another without waiting for a response signal corresponding to the transfer request signal itself to be received.

However, in this conventional case, there was no management means for managing the difference between the number of received transfer request signals and the number of transmitted transfer response signals.

Also. For some reason, for example, an undesired delay may occur in data transfer with a host device. Immediately after receiving a transfer request from a lower-level device, it may not be possible to return a transfer response signal as desired, and therefore it may be difficult to find a timing ≧ for instructing the end of data transfer.

[Problem to be solved by the invention]

In the conventional case, since the above-mentioned management means is not provided, there is a possibility that the transfer response signal to be returned cannot be returned correctly. Further, as described above, there are cases where the timing of returning the transfer response signal is undesirably delayed, and it is difficult to find the timing for instructing the end of data transfer.

For this reason, at the point when it receives a number of data transfer request signals corresponding to the number of data that it should receive (data can be considered to be transferred along with this signal). If the above data transfer end instruction signal is sent,
The data transfer end instruction signal may be sent first in a state where the transfer response signal that should be sent back cannot be sent back.

The present invention enables a device to send a data transfer end instruction signal upon receiving the number of data that it should receive, and to correctly return a data transfer response signal even if there is a delay in data transfer. It is an object.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. The code 1 in the figure is a channel processor (hereinafter also referred to as a channel device) 5
2 is a host device, and in the case shown, main memory i! f
(MS), and 3 is a lower-level device, which in the illustrated case is represented by an input/output device (■0).

Further, 4 is a data buffer. Furthermore, 5 is the request/response number difference stack created in the tree invention,
For example, as shown in the figure, in response to transfer request signals being issued one after another from the lower device 3 and data being accumulated in the data buffer 4, the channel device 1 sends a transfer response signal notifying that it has received the data. Although the signals are sent back sequentially, the difference between the number of received transfer request signals and the number of sent transfer response signals during this period is maintained.

In addition, 6 is a termination instruction status provided in the present invention, and even if the return timing of the transfer response signal is delayed for some reason as described above, the number of signals that should be received by the white receiver. A data transfer end instruction signal can be sent when a number of transfer response signals corresponding to the number of data are returned.

[Sakukawa] Now, it is difficult to transfer data from the lower-level device 3 to the higher-level device 2. In this case, the lower device 3 sends out data in response to the transfer request signal, and sends out the transfer request signals (along with the data) one after another without waiting for receipt of a transfer response from the channel device 1.

The transmitted data is temporarily stored in the data huffer 4 and then transferred to the host device 2. The channel device 1 returns a transfer response signal in response to receiving the individual transfer request signals.

The request/response count difference stack 5 is . By holding a value corresponding to the difference between the number of transfer request signals received and the number of transfer response signals sent, the number of transfer response signals that should be returned can be managed.

On the other hand, channel device 1 knows the number of data it should receive. When the number of transfer request signals corresponding to the data number N is received, the contents r of the request/response number difference stack 5 at this point in time are transferred to the end instruction stack 6. The value r indicated by the content is the value at the time when the number of transfer request signals corresponding to the number of data N is received. In order to return the number of transfer response signals corresponding to the number N, the number indicates the number of transfer response signals that should be returned after this point in time. Therefore, every time the channel device 1 returns a transfer response signal from now on, it increments the content r of the end instruction stack 6 by minus 1, so that it can send out the data transfer end instruction signal.

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention. In the figure, reference numeral 1 is a channel device (channel processor), 4 is a data buffer, 5 is a request/response number difference stack, 6 is an end instruction stack, 7 and 8 are respective data hashes, 9 is a hash control circuit, 10 11 is a response permission determination unit which determines whether or not to send a transfer response signal; 11 is a transfer request signal receiving circuit; 12 is a transfer response signal sending circuit; and 13 is a data transfer end instruction signal sending circuit. represents.

The contents of the request/response number difference stack 5 are incremented by +1 in response to reception detection by the transfer request signal receiving circuit 11, and -1 in response to transmission by the transfer response signal transmitting circuit 2. The response determination unit 10 determines the number of data currently stored in the data buffer 4 and the request/response number difference stack 5.
It is determined whether or not to send a transfer response signal, taking into consideration the content ({a) of . And if it should be sent. The transmission instruction is sent to the transfer response signal transmission circuit Fl&l2.

In addition, the response availability determination unit 10 knows the number N of data that the channel device 1 should receive, and when it receives the number of transfer request signals corresponding to the number N, the request/response number difference stack 5 at that time The contents (values) of are transferred to the end instruction stack 6.

The contents of the end instruction stack 6 are as follows. From then on. -1 in response to the transmission by the transfer response signal transmission circuit 12, for example, when the content becomes the value "work", the . Issue a termination instruction sending instruction.

Note that if a transfer response signal is not sent when sending a data transfer end instruction signal as in the case of a known IPI interface, the contents of the illustrated request response number difference stack 5 will be the same as when the data transfer end instruction signal is sent. is set to minus 1.

FIG. 3 shows a time chart 1- when the sending of the second transfer response signal is delayed, and FIG. 4 shows a time chart when the sending of the third transfer response signal is delayed.

As can be seen from FIGS. 3 and 4, if the number of data that the channel device 1 should receive is N=3,
When three transfer request signals are received, the contents of the stack 5 are transferred to the stack 6. In the case shown in Figure 3,
Since there is a delay in sending the second transfer response signal, the value "3" is transferred to the stack 6. Also the fourth
In the case shown in the figure, since there is a delay in sending out the third transfer response signal, the value "2" is transferred to the stack 6.

and. From then on. In response to the transmission of the transfer response signal, the contents of the stack 6 are incremented by -1.

When the contents of the stack 6 reach the value "1", an operation is activated to send out a data transfer end instruction signal.

As a result, the number of transfer response signals corresponding to the number of data to be received, N=3, is sent out. In other words, a data transfer end instruction signal is immediately issued, and subsequent transmission of transfer request signals is terminated.

In the conventional case, the termination instruction stack 6 does not exist. For example, if a data transfer end instruction signal is sent immediately upon receiving a transfer request signal corresponding to N=3, the data transfer end instruction signal will be sent before a predetermined number of transfer response signals are sent. It was something that was going to happen.

[Effects of the Invention] As explained above, according to the present invention, it is possible to send a data transfer end instruction signal under correct timing.

[Brief explanation of drawings]

FIG. 1 shows the principle structure of the invention, FIG. 2 shows the structure of an embodiment of the invention, and FIGS. 3 and 4 show time charts 1 and 4, respectively. In the figure, 1 is a channel device (channel processor) 4
2 is the upper device (main memory), 3 is the lower device (input/output device). 4 represents a data buffer, 5 represents a request/response count difference stanok, and 6 represents an end instruction stack.

Claims (1)

[Scope of Claims] A channel device (1) having a data buffer (4) for data transfer provided between a higher-level device (2) side and a lower-level device (3) side, the channel device (1) having a data buffer (4) for data transfer; Device(
3) In addition to performing synchronous transfer with the device, the device issuing the transfer request can agree in advance on the number of transfer request signals that can be sent out prior to receiving the transfer response signal, and issue the transfer response. A channel device (1
), creates a request/response number difference stack (5) that holds the difference between the number of received data that received the transfer request signal and the number of data sent that sent the transfer response signal, and also corresponds to the number of data that should be received by itself. The contents of the request/response number difference stack (5) upon receiving the number of transfer request signals to be received are transcribed, and for the number of transfer request signals corresponding to the number of data to be received by the self, A channel device characterized in that it has an end instruction stack (6) for sending out the data transfer end instruction signal when the channel device sends out the transfer response signal corresponding to the number.