JPH04295952A - Message communication equipment for multi-processor system - Google Patents

Abstract

PURPOSE:To execute the communication of message data at a high speed, and to hardly lower the ability of instantaneous message communication by eliminating an unnecessary copy operation. CONSTITUTION:In the message communication equipment in a multi-processor system, which has a shared memory 300, and executes to transmit and receive message data by a transmitting/receiving queue 300a by connecting plural memory blocks, a free memory block 301 of a free memory pool 300b in the shared memory 300 is used in common by an inter-task communication in a processor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device in a multiprocessor system, and more particularly to a message communication device in a multiprocessor system that increases the speed of message data communication.

0002

2. Description of the Related Art Conventionally, a message communication device in a multiprocessor system that uses a shared memory to send and receive message data has provided a communication channel on the shared memory and used the communication channel on the shared memory to transfer data. Devices that perform transmission and reception are known. This communication channel on the shared memory executes data transmission and reception using a so-called transmission/reception queue (transmission/reception queue) that is configured by connecting a plurality of memory blocks of the shared memory.

[0003] In such a message communication device in a multiprocessor system using a shared memory, there is a so-called mailbox method as a message communication method for a real-time system. This mailbox method extracts a memory block of an appropriate size from the memory pool of the operating system, copies outgoing message data to this memory block, and posts the data to a mailbox.

FIG. 5 shows a message data communication device in a conventional multi-processor system using shared memory. In FIG. 5, a transmitting processor 10 includes a central processing unit (CPU) 11, an operating system (OS) 12, and a driver 13, and a receiving processor 20 similarly includes a central processing unit (CPU) 21, Operating system (O
S) 22 and a driver 23.

A transmission/reception queue 30a is formed in the shared memory 30. The transmission/reception queue 30a is composed of a plurality of connected memory blocks 31, 32, 33, . . . 3n. Sending processor 10
Message data is transmitted and received between the receiving processor 20 and the receiving processor 20 using the transmitting/receiving queue 30a as a communication channel.

Consider now the case where message data is transmitted from the transmitting processor 10 to the receiving processor 20. In this case, task A of the sending processor 10 is
A memory block 121a of an appropriate size is acquired from the 12 memory pools 121, and this memory block 121
Write the message data to be sent to a, and write this as
For example, it is transmitted to the driver 13 via task C, and the driver 13 copies the contents of this memory block 121a to the memory block 31 of the shared memory 30.

In the shared memory 30, this memory block 3
The message data written in memory block 3n is sequentially moved to memory block 32 and memory block 33, and when this data reaches memory block 3n, the receiving processor 2
The driver 23 of 0 acquires a memory block 221a of an appropriate size from the memory pool 221 of the OS 22,
The configuration is such that the contents of the memory block 3n of the shared memory 30 are copied to this memory block 221a and transmitted to the task E via the task D, for example.

[0008]

[Problem to be Solved by the Invention] By the way, immediacy is important in real-time systems such as message communication devices, but in conventional devices such as those mentioned above, message communication requires memory acquired from the operating system's memory pool. Since memory blocks are used, when performing inter-processor communication using shared memory, it is necessary to copy the contents of the memory block acquired from the operating system's memory pool to the memory block of the shared memory. Retrieving received message data from memory requires copying the contents of a memory block in shared memory to a memory block obtained from the operating system's memory pool, resulting in time loss and impairing the immediacy of message communication. There was a problem that

This will be further explained using FIG. 6. In FIG. 6, inter-task communication within the sending processor 10 on the sending side uses a memory block 121a acquired from the memory pool 121 of the OS 12. here,
When performing inter-processor communication using the shared memory 30, the contents of the memory block 121a are copied to the memory block 4 at the first stage of the transmission/reception queue of the shared memory 30.

In the shared memory 30, when the contents of the memory block 121a are copied to the memory block 4 at the first stage of the transmission/reception queue, connection is made with the memory block 3 at the next stage, and message data is transmitted. When this message data reaches the memory block 1 at the last stage of the transmission/reception queue, it is disconnected from the memory block 2 at the previous stage.

Message data is retrieved from the shared memory 30 by copying the contents of the memory block 1 at the last stage of the transmission/reception queue to the memory block 221a acquired from the memory pool 221 of the OS 22. Inter-task communication within the receiving processor 20 on the receiving side uses the memory block 221a acquired from the memory pool 221 of this OS 22.

[0012] According to such a configuration, two copy operations are required: when transmitting message data from the sending side to the shared memory and when retrieving message data from the shared memory.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a message communication device in a multiprocessor system that speeds up message data communication by eliminating unnecessary copying operations and does not impair the immediacy of message communication. purpose.

[0014]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a multiprocessor having a shared memory and transmitting and receiving message data using a transmitting/receiving queue formed by connecting a plurality of memory blocks of the shared memory. The message communication device for the system is characterized in that the memory block of the shared memory is shared for communication between tasks within a processor.

[0015]

[Operation] The memory block of the shared memory used for inter-processor communication is also shared for intra-processor inter-task communication. This eliminates unnecessary copy operations and speeds up message data communication.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a data communication device in a multiprocessor system according to the present invention. In FIG. 1, the transmitter processor 1
00 is configured with a central processing unit (CPU) 101, an operating system (OS) 102, and a driver 103, and the receiving processor 200 similarly includes a central processing unit (CPU) 201, an operating system (OS) 202, It is configured to include a driver 203.

[0018] Also, within the OS 102 there is a memory pool 10.
2a, but in this embodiment, this memory pool 102
A is not used. In addition, memory pool 2 is also stored in the OS 202.
02a, but in this embodiment, this memory pool 20
2a is also not used.

In the shared memory 300, a transmission/reception queue 300a consisting of a plurality of connected memory blocks is formed, and an empty memory block queue (empty memory pool) 300b having an empty memory block 301 is further provided.

Next, the operation of this embodiment will be explained.

When task A of the sending processor 100 communicates message data, it acquires a free memory block 301 from the free memory pool 300b of the shared memory 300, writes message data to be sent to this memory block 301, and writes the message data to be sent to this memory block 301. is transmitted to the driver 13 via, for example, task C, and the driver 13 sets this memory block 301 as the first stage memory block of the transmission/reception queue of the shared memory 300 without copying it as is.

In the shared memory 300, this memory block 301 is connected to the next stage memory block of the transmission/reception queue, and this message data is sequentially moved. When this data reaches the last stage memory block, this memory block is copied. directly to the receiving processor 200 without
The task is sent to task D via the driver 203. Task D further transmits this to, for example, task E. This operation will be further explained with reference to FIG.

In FIG. 2, inter-task communication within the sending processor 100 on the sending side uses a free memory block 301 acquired from the free memory pool 300b of the shared memory 300 for inter-task communication. Here, when performing inter-processor communication using the shared memory 300, the memory block 301 is used as it is as the first-stage memory block 4 of the transmission/reception queue.

In the shared memory 300, the first stage memory block 4 of this transmission/reception queue is connected to the next stage memory block 3, and message data is transmitted. When this message data reaches the memory block 1 at the last stage of the transmission/reception queue, it is disconnected from the memory block 2 at the previous stage.

Then, this final stage memory block 1 is sent as is to the receiving side processor 200 on the receiving side, and this final stage memory block 1 is used as is for communication between tasks within the receiving side processor 200. I do.

[0026] According to such a configuration, unnecessary copying operations are eliminated and message data communication can be made faster.

FIG. 3 is a flowchart showing the operation of the driver 103 of the transmitting processor 100. In FIG. 3, first, a free memory block is acquired from the free memory pool 300b of the shared memory 300 (step 131). Subsequently, transmission data is created and written into this free memory block (step 132). Thereafter, this memory block is used to queue in the transmission/reception queue 300a of the shared memory 300 (step 133).

FIG. 4 is a flowchart showing the operation of the driver 203 of the receiving processor 200. In FIG. 4, first, when data reception is detected from the shared memory 300 (step 231), the memory block of the transmission/reception queue 300a of the shared memory 300 is dequeued (received) (step 232), and predetermined data reception processing is executed. (Step 233). Thereafter, the used memory block is returned to the free memory pool 300b of the shared memory 300 (step 234).

[0029]

As explained above, in this invention, the memory block of the shared memory used for inter-processor communication is also shared for intra-processor inter-task communication, so unnecessary copy operations are eliminated and message data This has the effect of increasing communication speed. and,
This effect becomes more pronounced as the length of transmitted and received message data increases.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a message communication device in a multiprocessor system according to the present invention.

FIG. 2 is an explanatory diagram illustrating a specific example of operation in the embodiment shown in FIG. 1;

FIG. 3 is a flowchart illustrating the operation of the transmitting device in the embodiment shown in FIG. 1;

FIG. 4 is a flowchart illustrating the operation of the receiving device in the embodiment shown in FIG. 1;

FIG. 5 is a block diagram showing a data communication device in a conventional multiprocessor system.

FIG. 6 is an explanatory diagram illustrating a specific example of operation in the conventional device shown in FIG. 5;

[Explanation of symbols]

10,100 Sending processor 11, 21, 1
01,201 Central processing unit (CPU) 12,22,102,202 Operating system (OS) 13,23,103,203 Driver 20,2
00 Receiving side processor 30, 300 Shared memory 31 to 3n Memory block 30a, 300a Transmission/reception queue 102a, 20
2a, 121, 221 memory pool 121a,
221a Memory block 300b Free memory block queue (free memory pool) 301 Free memory block

Claims (1)

[Claims] 1. A message communication device in a multiprocessor system that has a shared memory and executes message data transmission and reception using a transmission/reception queue formed by linking a plurality of memory blocks of the shared memory, wherein the memory blocks of the shared memory are connected to each other within a processor. A message communication device in a multiprocessor system, characterized in that the message communication device is shared in inter-task communication.