JPS61227451A - Integrated circuit for serial data communication control - Google Patents

Abstract

PURPOSE:To improve the efficiency of data transfer by providing a transmission data storage circuit, a line state supervisory terminal and a comparator circuit comprised of the content of the transmission data storage circuit with the result of supervision of the line state supervisory terminal to a control integrated circuit. CONSTITUTION:A transmission data input buffer 2 transfers a transmission data to a transmission data storage circuit 4. Further, the transmission data is transferred to a serial buffer 3 where the data is converted into a predetermined form serial data and outputted from a transmission data output terminal 8. The transmission data stored in the transmission data storage circuit 4 is inputted to a state comparator circuit 5 via a comparison data transfer line 10 and compared with a data in the sending state actually from the line state supervisory input terminal 11. If both the data are dissident, the state comparison circuit 5 outputs a dissidence detection display signal to a dissidence detection display line 12. Thus, whether or not the transmission data exists normally on a communication line is recognized by only checking the dissidence detection display line 12 at the sending side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for controlling serial data communication, and particularly to a large-scale integrated circuit for controlling serial data communication (hereinafter referred to as communication control LSI).

[Conventional technology]

FIG. 4 is a block diagram showing an example of a conventional communication control LSI. Normally, the L8I for communication control has separate transmitting and receiving sections and is capable of full-duplex operation.
The receiving section is not directly related to the present invention and will therefore be omitted. The transmission operation in the communication control L811' shown in FIG. 4 is performed as follows. That is, the process? Parallel transmission data written to the transmission data buffer 2 from a data bus 6 (not shown) is transferred to the serial buffer 3 through an internal bus 7. Here, the data is converted into serial data in a format predetermined by the communication protocol, and output as serial data from the transmission data output terminal 8. Therefore, the conventional communication control L
SI basically only had the function of converting parallel data into serial data and outputting it.

[Problem that the invention seeks to solve]

The conventional communication control LSI described above cannot detect such situations when noise occurs on the communication line or when the transmitting section of the communication control LSI becomes abnormal. There was a problem in that it was not possible to immediately determine whether or not the signal had correctly reached the receiving end through the line, or whether the transmission operation was being performed normally. Furthermore, even if the above-mentioned abnormal state occurs, the processor cannot recognize the state, so it will not be able to continue transmitting data to the communication control LSI, thereby preventing erroneous data on the receiving side. Therefore, in order to solve this problem, the sending side waits for a response signal from the receiving side after the transmission is completed, and the data is received normally. We use a method to check whether the line has arrived, but with this method, we cannot tell whether an error has occurred until after all data has been sent, and if the line becomes abnormal during the transmission, Since unnecessary data is transmitted, there is a drawback that data transfer efficiency decreases. In addition, it is necessary to prepare software to recognize the response signal, which may make the software complicated and reduce the efficiency of the entire system. Figure 5 shows a method to solve this problem. Sometimes methods are used. That is, FIG. 5 is a professional diagram showing another example of the conventional communication control LSI.
In this method, the transmission data output terminal 8 is connected to the own reception data input terminal 19. This communication control LS11
“Then, in advance, send the data to the memory in the system (
(not shown), the process reads the received data from the receiving operation of its own receiving unit 18 and compares it with the data in the memory, thereby preventing errors on the communication line. It becomes possible to immediately recognize whether or not it has occurred. However, since the processor must always read the received data and compare it with the transmitted data, there is a drawback that the software becomes complicated. Furthermore, since the receiving section 18 of the communication control LSI is used for the purpose of line monitoring rather than the intended receiving operation, there is a drawback that the usage efficiency of the communication control LSI is reduced.

[Means for solving problems]

The serial data communication control integrated circuit of the present invention includes a transmission data holding circuit for holding transmission data that is written from scratch in a process independent of a transmission data buffer, and a transmission data holding circuit for monitoring the data transmission status on a communication line. It includes a line state monitoring terminal and a comparison circuit that compares the contents of the transmission data holding circuit and the monitoring result of the line state monitoring terminal.

〔Example〕

Next, one aspect of the present invention will be explained using FIGS. 1 to 3.

FIG. 1 is a block diagram of a communication control LSI showing an embodiment of the present invention, in which a communication control LSI 1811 is a serial bus connected to a transmission data input buffer 2, a serial buffer 3, and a retained data transfer bus 9. , 7a 3, a status comparison circuit 5 connected to the transmission data holding circuit 4 through a comparison data transfer line 10, a data bus 6 having the same configuration as the conventional example, and an internal bus. 7. Transmission data output terminal 8
, a line status monitoring input terminal 11 for monitoring the data transmission status on the communication line, and a mismatch detection display line 12 for outputting a mismatch detection display signal from the status comparison circuit 5. In the figure, transmission data is written to a transmission data cover 7a 2 via a data bus 6 by a processor (not shown). The transmission data input buffer 2 transfers this transmission data to the transmission data holding circuit 4 via the held data transfer bus 9t-. In addition, this transmission data is transferred to the serial buffer 3 via the internal bus 7 in order to perform the original transmission operation, where it is converted into serial data in a predetermined format and output from the transmission data output terminal 8. .

The transmission data held in the transmission data holding circuit 4 is input to the state comparison circuit 5 via the comparison data transfer line 10, and is compared with the data in the actual transmission state of the line state monitoring input terminal 11. Here, if the two data do not match, the state comparison circuit 5 outputs a mismatch detection display signal to the mismatch detection display line 12.

Therefore, the transmitting side can recognize whether the transmitted data is normally on the communication line by simply checking the mismatch detection display line 12, and if an error occurs in the transmitted data,
The process can immediately stop sending operations.

Next, FIGS. 2 and 3 show the 1st part of the communication control L8I in FIG. 1, respectively. It is a professional drawing which shows a 2nd example of use. In FIG. 2, the transmission data output terminal 8 is connected to the connection line 13.
This is applied when the line status monitoring input terminal 1 is directly connected, and the transmission data output terminal 8 is directly connected to the other party. Further, in the second usage example shown in FIG. 3, the transmission data output terminal 8 is connected to the line interface circuit 14.
In this case, the communication line 15 is connected to the communication line 915 via the line interface circuit 14'.
It is only necessary to connect to the line condition monitoring input terminal 1 through the .

1 above. In the second usage example, when the data sent on the communication line is different from what was actually written by the processor, the status comparison circuit 5 detects this,
The transmission side is notified by the mismatch detection display line 12.

〔Effect of the invention〕

As explained above, the present invention detects and displays when the data actually transmitted on the communication line does not match the data that should be transmitted, so that the process can immediately stop the transmission operation. This has the effect of minimizing the reception of erroneous data on the receiving side and increasing the efficiency of data transfer. Furthermore, since there is no need to constantly monitor the process line, the software can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control LSI showing an embodiment of the present invention, and FIGS. FIG. 4 is a block diagram showing an example of a conventional communication control LSI, and FIG. 5 is a block diagram showing another example of a conventional communication control LSI. 1.1', 1"... LSI for communication control, 2...
...Transmission data input buffer, 3...Serial buffer, 4...Transmission data holding circuit, 5...
... Status comparison circuit, 6 ... Data bus, 7
...Internal bus, 8...Transmission data output terminal, 9...Bus for holding data transfer, 10...
... Comparison data transfer line, 11 ... Input terminal for line status monitoring, 12 ... Mismatch detection display line,
13... Connection line, 14, 14'...
line interface circuit, 15... communication line,
16... Input/output cover, fa, 17... Received data transfer bus, 18... Receiving section, 19.
...Receive data input terminal. (1,゛Wif Figure V;Z Figure 3rd

Claims (1)

[Claims] A serial data communication control integrated circuit including a transmission data input buffer, a transmission data holding circuit for holding transmission data written from a processor, a line state monitoring terminal for monitoring a data transmission state on a communication line, and the above-mentioned An integrated circuit for controlling serial data communication, comprising a comparison circuit that compares the contents of the transmission data holding circuit and the monitoring result of the line state monitoring terminal.