JP2000322375A - Fifo with dma control and dma transfer system and method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain quick and efficient data transfer by absorbing the difference of the data transferring speeds of buses with different data bus width. SOLUTION: An FIFO 107 with DMA control having two 32 byte FIFO whose one FIFO is connected with a 32bit data bus 105 and whose other FIFO is connected with a 16bit data bus 109 and an FIFO control part including a DMA controlling function receives data from an I/O device 108 to one FIFO by DMA transfer in response to a DMA request (REQ-B). The other FIFO receives data with one time DMA transfer burst length, and then loads the received data in one FIFO. After one FIFO receives the data, a DMAC 104 receive the data from one FIFO by DMA transfer in response to a DMA request (REQ-A) from the FIFO 107 with the DMA control. While one FIFO transmits the data to the DMAC 104, the I/O device 108 transmits the next data to the other FIFO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a system for performing data transfer by Memory Access, and particularly to a DMAC (DMA Controller) on the same bus.
The present invention relates to a transfer method using a FIFO when performing a DMA transfer between devices having different data bus widths.

[0002]

2. Description of the Related Art In the above-mentioned FIFO and DMA transfer systems, conventionally, when a DMA transfer is performed between a DMAC on the same bus and a device having a different data bus width, a DMA transfer is performed.
The data bus width was converted by sequentially writing data to each buffer memory using one buffer memory, and then reading data from the buffer memory at the same time. The time required for DMA transfer on the bus becomes long, making it difficult to perform high-speed and efficient data transfer.
Also, when performing DMA transfer between two different buses, FI
Although there is a method of relaying the FO, this FIFO requires a DMAC on each of two buses, and therefore cannot be used in the case of DMA transfer between devices on the same bus as in the present invention. .

Japanese Unexamined Patent Publication No. 7-152683 discloses a plurality of buffer memories and a write control circuit for controlling writing of the plurality of buffer memories between data buses having different bus widths. A buffer memory circuit characterized in that data having a smaller width is sequentially written to a plurality of buffer memories, and data written to the plurality of buffer memories is simultaneously output to a data bus having a larger bus width. I have.

Japanese Patent Application Laid-Open No. 10-293742 discloses that a first bus and a second bus which are different from each other
A data transfer method and apparatus are described, characterized in that DMA transfer is performed bidirectionally by connecting via a bus repeater such as an IFO.

[0005]

SUMMARY OF THE INVENTION A first object of the present invention is to provide a method for performing a DMA transfer in the above-mentioned prior art, while writing data having a narrower bus width sequentially to a plurality of buffer memories while performing a DMA transfer. A wide data bus is also used for this DMA.
In view of the fact that it is necessary to occupy the bus for transfer and it is difficult to perform high-speed and efficient data transfer,
Bit width convertible bidirectional FIF with built-in control function
By using O, the difference in the data transfer speed of each bus is absorbed, and high-speed and efficient data transfer is performed.

A second object is that in the prior art,
In consideration of the fact that data cannot be transmitted to a data bus having a wide bus width while data having a narrow bus width is being sequentially written to a plurality of buffer memories, a bit width conversion incorporating the DMA control function is considered. An object of the present invention is to configure a plurality of FIFO blocks inside a possible bidirectional FIFO to enable mutual data exchange, thereby performing simultaneous transmission / reception operations and performing faster and more efficient data transfer.

A third object is that, in the above-described prior art, when performing DMA transfer, even if the setting of the DMAC is the same, depending on the address at which the transfer is started, the odd number of bytes at the beginning and end of the transfer is determined. May be transferred,
In view of the necessity of adjusting the address and eliminating the transfer of an odd number of bytes, a bidirectional FIFO having a built-in DMA control function and capable of converting the bit width is used.
By setting the number of transfer bytes of the IFO to be programmable according to the transfer burst length of the DMAC, it is possible to correspond to the transfer burst length of an arbitrary DMAC.

A fourth object of the present invention is that, in the prior art, when performing a DMA transfer, when a buffer memory circuit suitable for an arbitrary bus width is configured, it is difficult to transfer data with another bus width. In view of the above, by making the bit width of the FIFO programmable, there is no need to specify the width of the bus to be connected, and data can be transferred between any data buses without changing the circuit.

[0009]

According to a first aspect of the present invention, in a data transfer by DMA between devices having different bit widths on the same bus, both devices capable of converting a bit width with a built-in DMA control function between the devices. The present invention relates to a DMA transfer method for relaying data by a FIFO.

[0010] The invention according to claim 2 is the DM according to claim 1.
A bit width convertible bidirectional FIFO having a built-in DMA control function used for the A transfer method,
The present invention relates to a FIFO having a plurality of blocks.

According to a third aspect of the present invention, in the data transfer by DMA between devices having different bit widths on the same bus, the internal FIFO according to the second aspect is used between the devices.
DMA relaying by FIFO with multiple blocks
The transfer method.

According to a fourth aspect of the present invention, in the data transfer by DMA between devices having different bit widths on the same bus, the internal FIFO according to the second aspect is used between the devices.
DMA relaying by FIFO with multiple blocks
It is a transfer system.

According to a fifth aspect of the present invention, the DM of the first aspect is provided.
In the A transfer method, the number of transfer bytes of a bidirectional FIFO with a built-in DMA control function and capable of converting a bit width can be set programmably.

According to a sixth aspect of the present invention, there is provided a digital camera according to the first aspect.
In the MA transfer system, the bit width of a bidirectional FIFO capable of converting the bit width incorporating the DMA control function can be set programmably.

[0015]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the DMA transfer system of the present invention. In this figure, 10
1 is a central processing unit (CP) for controlling this system.
U). Reference numeral 102 denotes a system controller for constructing this system together with the CPU 101.
It has a PU bus interface and a memory device interface, and may include a DMAC. Reference numeral 103 denotes a memory for storing data, and usually a DRAM is used.

A DMAC 104 controls DMA transfer.
It is. The DMA transfer is performed when the DMAC 104
01 and the memory 103 and the I / O device 108
Data transfer between the two. 105 is 32 bi
t is a data bus having a width of 32 bits, and having a data bus width of 32 bits.
The AC 104 and the FIFO with DMA control 107 are connected. Reference numeral 106 denotes various control signals generated by the system controller 102, such as an address bus, an RD signal, and a WR signal.
Signal, CS signal and the like.

Reference numeral 107 denotes two 32-byte FIs internally.
DM with FIFO control unit including FO and DMA control functions
FIFO with A control, one FIFO is 32 bits
The other FIFO is 16 bits on the data bus 105
It is connected to the data bus 109. 108 is 16b
I with data bus and DMA interface
/ O device. A data bus 109 has a 16-bit width, and connects the I / O device 108 having a 16-bit data bus width to the FIFO 107 with DMA control.

Reference numeral 110 denotes a signal (ACK-A) output when the DMAC 104 performs a DMA transfer with the FIFO 107 with DMA control, and transmits and receives data in synchronization with this signal. 111 is a FIFO1 with DMA control
Reference numeral 07 denotes a signal (REQ-A) for requesting the DMAC 104 to transmit and receive data. Reference numeral 112 denotes a case where the FIFO with DMA control 107 performs DMA transfer with the I / O device 108.
This signal (ACK-B) is output when data is transferred, and data is transmitted and received in synchronization with this signal. 113 is I
This is a signal (REQ-B) that requests the / O device 108 to transmit and receive data to and from the FIFO 107 with DMA control.

In the above system configuration, DMAC1
Assuming a case where data transfer by DMA is performed between the I / O device 04 and the I / O device 108,
07 will be described in detail.

FIG. 2 shows the FIF with DMA control in FIG.
It is a block diagram which shows a structure of O107. 201 is F
This is a FIFO unit composed of the FIFO-A 203 and the FIFO-B 204, and the FIFO-A 203 and the FIFO-B
204 can load data with each other. FIF
The input of the O-A 203 is connected to the 32-bit data bus 105, and the output of the FIFO-A 203 is connected to the 32-bit data bus 105 via the three-state buffer 210.

The input of the FIFO-B 204 is 16
connected to the bit data bus 109 and the FIFO-B20
The output of 4 is 16b via the 3-state buffer 211.
It is connected to the data bus 109. 202 is F
This is a FIFO control unit including an IFO control register 205, a transfer byte number register 206, a transfer byte counter A207, and a transfer byte counter B208 (for details, see FIG. 6). Reference numeral 209 denotes a bypass switch that relays the 32-bit data bus 105 and the 16-bit data bus 109. The bypass switch 209 can directly connect the 32-bit data bus and the 16-bit data bus by the BypsOe signal controlled by the FIFO control register 205.

Also, three-state buffers 210 and 211
By inputting the BypsOe signal and the Dir signal controlled by the FIFO control register 205 to the enable line, the data transfer direction is controlled.

FIG. 3 is a block diagram showing the internal configuration of the FIFO unit 201 in FIG. FIFO-A20
3. The FIFO-B 204 is a 32-byte FIFO in which memory cells each having 32 latches are connected in eight stages.
Each memory cell can change the data bus width to 8 bits, 16 bits, or 32 bits by a selector control signal, and determines whether the input of the memory cell is the output of the preceding memory cell or the loading of data from the reception FIFO. It can be switched (see FIGS. 4 and 5 for details).

The latch timing of each FIFO differs depending on the data transfer direction. When the data transfer direction is A → B (Dir = 1), the FIFO-A 203
Is the rising edge of the signal ACK-A, FIFO-B
Reference numeral 204 denotes a falling edge of the signal ACK-B, and when the data transfer direction is B → A (Dir = 0), FIFO-A
203 is a falling edge of the signal ACK-A, FIF
The OB 204 latches data at the rising edge of the signal ACK-B.

FIG. 4 is a block diagram showing the internal structure of each memory cell in FIG. Reference numeral 401 denotes a latch unit composed of 32 latches, and ACK-A, / ACK
-A (inversion of ACK-A), ACK-B, / ACK-B
Input data is latched at the rising edge of each signal of (ACK-B inversion). Reference numeral 402 denotes an input selector unit for selecting data to be input to the latch 401, and switches which of the data to be input to the latch by a selector control signal. An output selector 403 selects an output destination of the data output from the latch 401.
To which of the output destinations to output the data is switched by the selector control signal.

FIG. 5 is a diagram showing a latch configuration pattern inside the memory cell of FIG. 4 according to the setting of the selector control signal. When data is to be loaded from the FIFO-A 203 to the FIFO-B 204 or from the FIFO-B 204 to the FIFO-A 203 (condition c501), the input selector 402 and the output selector 403 are selected. , Data from one FIFO is set.

When the FIFO is connected to the 32-bit data bus and the data of the preceding memory cell is latched (condition c502), the input selector 402 and the output selector 403 are selected, and the latch is selected. 4
01 is input to the data (bit) of the preceding memory cell.
(31: 0)) is set. And FIFO is 1
When the data of the memory cell at the previous stage is latched when connected to the 6-bit data bus (condition c503), the input selector 402 and the output selector 403 are selected, and the (bit (31:24 ), B
The data (bit (15: 0)) of the preceding memory cell is set to the input of it (23:16), and the data (bit (15: 8), bit (7: 0)) of the latch unit 401 is set. The input includes (bit (31:24),
bit (23:16)) is set.

Further, when the FIFO is connected to the 8-bit data bus and the data of the preceding memory cell is to be latched (condition c504), the input selector 402 and the output selector 403 are selected, and the latch is selected. 4
01 (bit (31:24)) is set with the data (bit (7: 0)) of the memory cell at the preceding stage,
The output of (bit (31:24)) of the latch unit 401 is set to the input of (bit (23:16)) of the latch unit 401, and the (bit (15:15:
8)), the input of (bit (23:
16)) is set, and (bi) of the latch unit 401 is set.
t (7: 0)) is input to the (bit)
(15: 8)) is set.

FIG. 6 is a diagram for explaining the operation of each block of the FIFO control unit in FIG. The FIFO control register 205 is a register that determines the operation mode of the FIFO. The transfer byte number register 206
This is a register for setting a burst length to be performed in one DMA transfer, and controls a transfer byte counter A 207 and a transfer byte counter B 208, which will be described later, based on the set value to change the burst length in a programmable manner. The transfer byte counter A 207 is a counter for counting the signal ACK-A output from the DMAC 104, and the transfer byte counter B 208 is a counter for counting the signal A output from the FIFO.
This is a counter for counting CK-B. The statuses of the FIFO-A and FIFO-B are determined based on the respective counter values, and the selector control signal, the signal REQ-A, and the signal A are determined.
The output timing of CK-B is controlled.

The initial values of the transfer byte counter A 207 and the transfer byte counter B 208 are different depending on the data transfer direction. When the FIFO receives data,
The number of receptions is set. When the FIFO transmits data, the initial value is 0, and the FIFO
When the transmission data is loaded from O, the number of transmissions is set. The number of receptions and the number of transmissions are set based on the value of the transfer byte number register 206.

FIG. 7 shows a DMA on the 32-bit bus shown in FIG.
I / O device 108 on 16-bit bus from C104
5 is a flowchart in a DMA transfer to. First,
FIFO 107 with DMA control from I / O device 108
Request (output signal REQ-B) (step S701). The FIFO with DMA control 107 outputs the signal R
After receiving the EQ-B, the DMAC 104 issues a DMA request (outputs the signal REQ-A) to the DMAC 104 (step S70).
2).

DMAC 104 receiving signal REQ-A
Transmits data to the FIFO-A 203 by DMA transfer (step S703). FIFO-A203 is 1
After receiving data for the number of DMA transfer bursts, F
The received data is loaded into the IFO-B 204 (step S704). After receiving the data, the FIFO-B 204 transmits the data to the I / O device 108 by DMA transfer (step S705). FIFO-B204
Is transmitting data to the I / O device 108, and at the same time, the DMAC 104 transmits the next data to the FIFO-A 203 (steps S701 to S703).

FIG. 8 shows the I / O from the DMAC 104 of FIG.
FIG. 6 is a timing chart of DMA transfer from a 32-bit data bus to a 16-bit data bus in a DMA transfer to the device 108. First, as an initial setting, the transfer byte number register 206 is set in accordance with the setting of the burst length of the DMAC 104 (set to 32 bytes in this embodiment).

The FIFO control register 20
5, FIFO mode switching bit = 0 (configuration mode), Dir = 1 (A → B), BypsOe
= 0 (no bypass), FIFO-A bit width conversion =
2 (32 bit width), FIFO-B bit width conversion = 1
(16-bit width), only the FIFO mode switching bit is set to 1 (operation mode). With this initialization, the FIFO with DMA control 107 enters the Ready state, the count values of the transfer byte counter A 207 and the transfer byte counter B 208 are set to 8, 0, respectively, and the signal REQ-B from the I / O device 108 is output. Wait for assert.

At timing t801, the signal REQ-B is asserted and the value of the transfer byte counter A207 at that time is 8 (FIFO-A is empty).
The FO asserts the signal REQ-A to the DMAC 104 (timing t802). The DMAC 104 that has received the signal REQ-A synchronizes with the signal ACK-A,
Data is output to a 2-bit data bus. FIFO-A
Reference numeral 203 denotes a rising edge of the signal ACK-A, which latches data, and the transfer byte counter A 207 is decremented by -1 to 7 (timing t803).

Since the DMAC 104 has a burst length of 32 bytes, it outputs the signal ACK-A eight times in total. FI
When the FO-A 203 receives the signal ACK-A eight times, the FO-A 203 enters a data full state, and the transfer byte counter A 207 becomes 0 (timing t804). When the value of the transfer byte counter A 207 becomes 0, the value of the transfer byte counter B 208 at that time is confirmed.
Since B204 is empty, FIFO-B2
The input of each latch of 04 is switched to the FIFO-A side, and the value of the transfer byte counter B208 is set to 16 (timing t805). Transfer byte counter B208
Is set to 16, at the falling edge of the signal ACK-B, the FIFO-B 204
3 is latched, and the data is output to the 16-bit data bus (timing t806).

At the next rising edge of the signal ACK-B, the value of the transfer byte counter A 207 is reset to 8, and the input of each latch of the FIFO-B 204 is changed to FIFO-B.
Switching to the preceding stage of B204 (timing t80
7). When the value of the transfer byte counter A207 is 8 (FIFO
-A is empty), the FIFO
Confirms the state of the signal REQ-B at that time,
If the signal is still asserted, the signal REQ-A is asserted to the DMAC 104 (timing t808).
The DMAC 104 receiving the signal REQ-A again outputs the next data in synchronization with the signal ACK-A (timing t809).

The FIFO-A 203 receives the signal ACK-A eight times, and the value of the transfer byte counter A 207 becomes 0 (data full state). At this time, the value of the transfer byte counter B 208 is not 0 ( Since data still remains in the FIFO-B), the input of each latch of the FIFO-B 204 is not switched to the FIFO-A side (timing t810). When the value of the transfer byte counter B208 becomes 1, the input of each latch of the FIFO-B204 becomes F
Switching to the IFO-A side, the transfer byte counter B2
The value of 08 is set to 16 (timing t811). When the value of the transfer byte counter B208 is set to 16,
At the falling edge of the signal ACK-B, FIFO-B2
04 latches the data of the FIFO-A 203 and 16
Data is output to the bit data bus (at timing t8).
12).

At the next rising edge of the signal ACK-B, the value of the transfer byte counter A 207 is reset to 8, and the input of each latch of the FIFO-B 204 is changed to FIFO-B.
Switching to the preceding stage of B204 (timing t81
3). If the transfer byte counter A 207 is not 0 at timing t811 (the FIFO-A 203 is not full), the value of the transfer byte counter B 208 is 0 (F
IFO-B 204 is empty), and waits until transfer byte counter A 207 becomes 0. The above is repeated from timing t814.

FIG. 9 shows the I / O on the 16-bit bus shown in FIG.
DMAC 104 on 32-bit bus from device 108
5 is a flowchart in a DMA transfer to. First,
From the I / O device 108, the FIFO 10 with DMA control
7, a DMA request (outputs the signal REQ-B) is made (step S901). Upon receiving the signal REQ-B, the FIFO with DMA control 107 transmits the FIFO from the I / O device 108 to the FIFO.
The OB 204 receives the data by DMA transfer (step S902). The FIFO-B 204 has one DMA
After receiving the data for the transfer burst length, the FIFO-A
203 is loaded with received data (step S90)
3). After the FIFO-A 203 receives the data,
DMA from FIFO 107 with MA control to DMAC 104
Make a request (output signal REQ-A) (step S90)
4). The DMAC 104 that has received the signal REQ-A
The data is received by DMA transfer from the IFO-A 203 (step S905). FIFO-A203 is DMAC
At the same time as transmitting the data to the I / O device 104, the I / O device 108 transmits the next data to the FIFO-B 204 (steps S901 to S902).

FIG. 10 is a timing chart of the DMA transfer from the 16-bit data bus to the 32-bit data bus in the DMA transfer from the I / O device 108 to the DMAC 104 in FIG. First, as an initial setting, the transfer byte number register 206 is set in accordance with the setting of the burst length of the DMAC (set to 32 bytes in this embodiment). Further, the FIFO control register 205 is
Mode switching bit = 0 (configuration mode), Dir = 0 (B → A), BypsOe = 0 (no bypass), FIFO-A bit width conversion = 2 (32b
it width), FIFO-B bit width conversion = 1 (16 bit
Width), only the FIFO mode switching bit is 1
(Operation mode).

In this initial setting, this FI with DMA control
The FO 107 is in the Ready state, the initial values of the transfer byte counter A 207 and the transfer byte counter B 208 are set to 0 and 16, respectively, and the I / O device 1
From 08, it waits for the assertion of the signal REQ-B. At timing t1001, the signal REQ-B is asserted, and the value of the transfer byte counter B208 at that time becomes 16 (FIFO-
B is empty), the FIFO outputs a signal ACK-B to the I / O device 108 and outputs the signal AC
The I / O device 108 receiving the KB receives the signal ACK-
Data is output to the 16-bit data bus in synchronization with B.

The FIFO-B 204 latches data at the rising edge of the signal ACK-B, and the transfer byte counter B 208 is decremented by 1 to 15 (timing t1002). Since the burst length of the DMAC 104 is 32 bytes, the FIFO is FIFO-
Until B204 becomes full, the signal ACK-B is output 16 times and data is received. When the signal ACK-B is output 16 times, the transfer byte counter B208 becomes 0 (timing t1003). Transfer byte counter B208 is 0
, The value of the transfer byte counter A 207 at that time is checked, and if it is 0, the FIFO-A 203 is empty, so the input of each latch of the FIFO-A 203 is switched to the FIFO-B side, and the transfer byte The counter A 207 is set to 8 (timing t1004).
When the value of the transfer byte counter A207 is set to 8,
The FIFO sends a signal REQ-A to the DMAC 104.
Is asserted (timing t1005).

DMAC 104 receiving signal REQ-A
Outputs the signal ACK-A, so that at the falling edge of the signal ACK-A, the FIFO-A 203
Latch the data of -B204 and output the data to the 32-bit data bus (timing t1006). At the next rising edge of the signal ACK-A, the transfer byte counter B208 is reset to 16, and the input of each latch of the FIFO-A 203 is switched to the preceding stage of the FIFO-A (timing t1007). Transfer byte counter B20
Since 8 has been reset to 16 (FIFO-B 204 is empty), the FIFO checks the state of signal REQ-B at that time and if it is still asserted, I
The signal ACK-B is output to the / O device 108 to receive the next data (timing t1008).

The FIFO-A 203 outputs the signal ACK-A eight times, and the transfer byte counter A 207 becomes 0 (data is empty). At this time, the transfer byte counter B
Since 208 is not 0 (the FIFO-B 204 is still receiving data), the input of each latch of the FIFO-A 203 is not immediately switched to the FIFO-B side, and it is necessary to wait until the transfer byte counter B 208 becomes 0. (Timing t1009). Thereafter, the process is repeated from timing t1003.

[0046]

According to the present invention, between devices having different bit widths, the data is transferred at the bit width of each device by relaying the FIFO and performing the DMA transfer. Therefore, it is not necessary to perform data transfer according to the above, and high-speed and efficient data transfer becomes possible.

By constructing a plurality of internal FIFO blocks, when one FIFO is transmitting data, the other FIFO can receive data. Good data transfer becomes possible.

Further, by making the number of transfer bytes of the FIFO programmable, the DMA transfer can be performed for any transfer burst length setting of the DMAC.

Further, by making the bit width of the FIFO programmable, it is not necessary to specify the bit width of the device to be connected, and DMA transfer between any devices can be performed without changing the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a DMA transfer system of the present invention.

FIG. 2 is a block diagram of a FIFO with a DMA control in FIG. 1;

FIG. 3 is a block diagram of a FIFO unit incorporated in the FIFO with DMA control in FIG. 2;

FIG. 4 is a block diagram showing an internal structure of a memory cell unit constituting the FIFO unit in FIG. 3;

5 is a diagram showing a latch configuration pattern inside a memory cell constituting a FIFO unit in FIG. 4;

FIG. 6 is a diagram illustrating the operation of each block constituting a FIFO control unit built in the FIFO with DMA control in FIG. 2;

FIG. 7 shows a 16-bit data bus of the present invention.
FIG. 4 is a flowchart of a DMA transfer process to a bit data bus.

FIG. 8 shows a 16-bit data bus according to the present invention;
FIG. 4 is a timing chart when a DMA transfer to a bit data bus is performed.

FIG. 9 shows a case where a 16-bit data bus according to the present invention uses 32
FIG. 4 is a flowchart of a DMA transfer process to a bit data bus.

FIG. 10 shows a diagram of a 16-bit data bus according to the present invention.
FIG. 4 is a timing chart when a DMA transfer to a 2-bit data bus is performed.

[Explanation of symbols]

101: central processing unit (CPU), 102: system controller, 103: memory, 104: DMAC,
105: 32-bit width data bus, 106: various control signals, 107: FIFO with DMA control, 108: I / O device, 109: 16-bit width data bus, 201: F
IFO, 202: FIFO control unit, 203: FIFO-
A, 204: FIFO-B, 205: FIFO control register, 206: transfer byte number register, 207
.., Transfer byte counter A, 208, transfer byte counter B, 209, bypass switch, 210, 211, 3-state buffer, 401, latch unit, 402, input selector unit, 403, output selector unit

Claims (6)

[Claims] 2. A data transfer method according to claim 1, wherein said DMA transfers data between devices having different bit widths on the same bus by means of a bit width convertible bidirectional FIFO having a built-in DMA control function. Transfer method. 2. A bidirectional FIFO having a built-in DMA control function for use in the DMA transfer system according to claim 1 and capable of converting a bit width, wherein a plurality of internal FIFO blocks are provided. . 3. A DMA transfer method in which data is transferred between devices having different bit widths on the same bus by DMA using the FIFO according to claim 2. 4. A DMA transfer system for relaying data between devices having different bit widths on the same bus by means of a FIFO according to claim 2, in a DMA transfer. 5. The DMA transfer system according to claim 1, wherein the number of transfer bytes of a bidirectional FIFO having a built-in DMA control function and capable of converting a bit width can be set programmably. system. 6. The DMA transfer system according to claim 1, wherein a bit width of a bidirectional FIFO having a built-in DMA control function and capable of converting a bit width can be set programmably. .