JPH0337221B2 - - Google Patents

Description

Detailed Description of the Invention The present invention expands the bus by connecting a plurality of bidirectional buses, each of which is connected to a central processing unit, main memory, and input/output device, through a bus coupling circuit. This invention relates to a bus configuration system that allows devices to transfer data across buses.

FIG. 1 shows an example of a system configuration when the input/output bus is expanded in a conventional information processing system. In FIG. 1, 1 is a main memory (MM) that stores instruction words and various data, 2 is a central processing unit (CPU) that controls execution of instructions, 3 to 6 are input/output devices (IO), and 7, 8 is the input/output bus (IOB ₀ , IOB ₁ ) that connects the CPU and each IO, 9 is the input/output bus 0
This is a bus coupling circuit (BUS CUP) that couples the (IOB ₀ ) 7 and the input/output bus 1 (IOB ₁ ) 8. In a general information processing system, one input/output bus is sufficient, but when the number of input/output devices increases or the bus cable length exceeds the limit value, electrical conditions and speed In order to satisfy the conditions, the bus coupling circuit 9 is connected to expand the input/output bus. FIG. 2 shows an example of the internal configuration of the bus coupling circuit 9, and 10 is the input/output bus 0 in FIG.
Bidirectional data line 0 forming part of (IOB ₀ )
(DATA ₀ ) and usually consists of multiple bits. 11
receives the above DATA ₀ and sends DATA ₁ 12 of IOB ₁
This is a relay bus driver that retransmits data to the 1-bit bus driver.

13 receives the above DATA ₁ 12 and reads IOB ₀ .
This is a relay bus driver that retransmits data to DATA ₀ 10, and is shown as a representative bus driver for only 1 bit in the figure. 14 is a control signal (BSI ₀ ) that defines the transfer direction of the data lines 0 and 1.
Then, it is sent from CPU2. 15 is the above BSI ₀
This is a bus driver that receives and resends it to BSI ₁ 19 of IOB ₁ .

Additionally, the BSI ₀ mentioned above is sent to each input/output device connected to the input/output buses 0 and 1, and specifies the data transfer direction between the input/output device and the CPU.
It is used as a control signal for the bidirectional bus driver in the bus coupling circuit 9. 16 and 17 are control terminals of the bus drivers 11 and 13, and the logic is "1".
When the input data is input, the contents of the input data are reproduced and sent out as output data, and when the logic "0" is input, the bus driver outputs the logic "0" regardless of the input data.

In the example in Figure 2, BSI ₀ 14 is bus driver 1.
It is connected to the control terminal 17 of No. 3 and the inverter circuit 18 . Further, the output of the inverter circuit 18 is connected to the control terminal 16 of the bus driver 11. Now, assuming that BSI ₀ is in the logic "1" state, the bus driver 13 has a control terminal input in the logic "1" state.
Therefore, the contents of DATA ₁ 12 are bus driver 1.
3, it is reproduced and sent to DATA ₀ 10. on the other hand,
Since the negative logic output of BSI ₀ 14 is connected to the control terminal 16 of the bus driver 11 by the inverter circuit 18, a logic "0" is input, and the output of the bus driver 11 is a logic "0" regardless of the contents of DATA ₀ . 0” is output.

Note that DATA ₀ 10 is wired-ORed with the outputs of the CPU 2, the bus drivers (not shown) of the input/output devices 3 and 4, and the bus driver 13 of the bus coupling circuit 9 in FIG. Only the bus drivers in the bus become enabled and send out meaningful information. The bus drivers of other devices are in an invalid state and are outputting logic "0". When using a bus driver with a normal TTL circuit configuration, logic “0”
is set to high level and logic "1" is set to low level. Similarly, for DATA ₁ 12, the outputs of the bus driver 11 of the bus coupling circuit 9 and the bus drivers of the input/output devices 5 to 6 are wired-ORed.

Therefore, as mentioned above, BSI ₀ 14 is logic “1”
In this case, the output of the bus driver 11 is logic “0”
(high level) is output, but due to the electrical characteristics of wired-or, the bus driver of one of the input/output devices 5 to 6 outputs logic “1” to DATA ₁ 12.
(low level), the value of DATA ₁ 12 becomes logic “1” (low level), and the bus driver of the input/output device outputs logic “0” (high level) to DATA ₁ 12. If so, DATA ₁ 12
The value of is fixed to logic "0". That is, DATA ₁ 1
The contents of 2 are the contents of the output of the driver of the input/output device described above. On the other hand, DATA ₀ 10
According to the operation described above, the contents of DATA ₁ 12 are outputted from the bus driver 13.

At this time, since the output of the bus driver of each device connected to DATA ₀ 10 is controlled to output logic "0", the value of DATA ₀ 10 is the output of the bus driver 13, that is, DATA ₁ 12. The content is confirmed. Also, the BSI ₀ 14 is logic “0”
In this case, the contents of DATA ₀ 10 are sent to DATA ₁ 12 according to the same control contents.

Next, 20 in FIG. 2 is an address sending signal (ADO ₀ ) sent from the CPU 2, which specifies that the content of DATA ₀ 10 is an input/output device address. 21 receives the above ADO ₀ 20 and ADO ₁ 22
This is a bus driver that retransmits data to Reference numeral 23 indicates a response signal (RPI ₁ ) sent from each of the input/output devices 5 to 6 in FIG. 24 is a bus driver that receives the above-mentioned RPI ₁ 23 and retransmits it to RPI ₀ 25.

In addition, the RPI ₀ 25 has the input/output device 3 shown in FIG.
The response signal sent from ~4 is also connected, and the CPU
Received by 2. Although the bus coupling circuit 9 has been schematically explained above with reference to FIG. 2, in reality, the bus coupling circuit 9 accommodates various control signals in addition to the signals mentioned above, and is provided with a bus driver, but this is omitted in FIG. are doing.

Next, an overview of the operation of an example of information transfer between the CPU 2 and the input/output device 6 shown in FIG. 1 will be explained.
FIG. 3 shows the transfer sequence at the time of the above-mentioned information transfer. In FIG. The transfer sequence when reading data from to CPU2 is shown. First, a case in which data is transferred from the CPU 2 to the input/output device 6 (the example shown in the figure shows the transfer of address information) will be described using FIG. 3a.
First, the data 31 to be sent out by the DATA sending bus driver (not shown) of the CPU 2 (Fig. 3a)
This shows a case where the input/output device address (IOA) and the register number (IOR) in the input/output device are transferred. ) to DATA ₀ 10. Then
The CPU 2 sends a logic " ₁ " signal to the ADO ₀ 20 at the _timing shown at 32 in FIG. ” to specify that the content of DATA ₀ 10 is address information. In this case, since the data is sent from the CPU 2, the above-mentioned BSI ₀ 14 is sent out as logic "0". (Not shown in FIG. 3a) Therefore, as described above, the information 3 sent from the CPU 2
1 propagates on DATA ₀ 10 and is retransmitted to DATA ₁ 12 via bus coupling circuit 9. In FIG. 3, the timing 33 is shown after a certain delay time (the same holds true for the sum of the propagation delay time on DATA ₀ 10 and the operation time of the bus driver 11). Also,
The ADO ₀ signal 32 is the bus driver 21 in FIG.
is retransmitted on ADO ₁ 22. In FIG. 3, timing 34 is shown after a certain delay time.

By the operation explained above, input/output bus IOB ₀ 7 and
The above-mentioned signals are sent to _IOB18 from the CPU2. On the other hand, input/output buses IOB ₀ 7 and IOB ₁ 8
The input/output devices 3 to 6 connected to ADO ₀ 20
Or, the content of ADO ₁ 22 receives a logic "1" state, compares the input/output device address (IOA) information on DATA ₀ 10 or DATA ₁ 12 with its own input/output device address, and selects a matching input/output device. The device stores information on DATA ₀ 10 or DATA ₁ 12 into internal registers (not shown). Hereinafter, a case will be described in which the input/output device 6 matches the IOA sent from the CPU 2 with its own input/output device address. The input/output device 6 is the above-mentioned DATA ₁ 12
If the above information is successfully received, the response signal is sent to the third
It is sent onto the RPI ₁ 23 at the timing shown at 35 in the figure. The response signal of RPI ₁ 23 is retransmitted to RPI ₀ 25 by driver 24 of bus coupling circuit 9 shown in FIG. This signal is referred to as timing 3 in Figure 3.
6. Next, when the CPU 2 receives the response signal 36 on RPI ₀ , it assumes that the sending information has been successfully received by the specified input/output device, and sends out the information to DATA ₀ 10 and ADO ₀ 20 previously. The transmission of signals 31 and 32 in FIG. 3 is completed.
The termination status of these signals is propagated to DATA ₁ 12 and ADO ₁ 22 by bus driver 11 and bus driver 21 of bus coupling circuit 9 in the manner described above. The input/output device 6 finishes sending the response signal 35 after confirming that the ADO ₁ 22 has become logic "0".

Through the operations described above, the information transfer sequence from the CPU 2 to the input/output device 6 is completed. Next, a transfer sequence for transferring information from the input/output device 6 to the CPU 2 will be explained with reference to FIG. 3b.
In this case, it is assumed that the selection of the input/output device 6 and the designation of the input/output operation have been completed by the transfer sequence shown in FIG. 3a described above. First, a read instruction signal for specifying reading of data from the CPU 2 is sent to the BSI ₀ 14 at the timing shown at 37 in Figure 3b.
Sends a logic “1” signal to. The signal is retransmitted by the bus driver 15 of the bus coupling circuit 9 to the BSI ₁ 19 at the timing shown at 38 in FIG. 3b.
Further, the read instruction signal 37 enables the bus driver 13 of the bus coupling circuit 9 and disables the other bus drivers 11,
A state is set in which the contents of DATA ₁ 12 are propagated to DATA ₀ 10 via the bus driver 13. Then, after receiving the read signal 38 on the BSI ₁ 19, the input/output device 6 sends the previously designated data onto the DATA ₁ 12 at timing 39 in FIG. 3b. The data is transferred via the bus driver 13 onto the DATA ₀ 10 in the manner described above.
It is propagated at timing 40 in Figure b. Next, the input/output device 6 sends a response signal for the data 39 after a certain period of time to the RPI ₁ 23 at timing 41 in FIG. 3b. The signal 41 is retransmitted by the bus driver 24 to the RPI ₀ 25 as a response signal 42. After receiving the response signal 42 and the contents of the data 40 on DATA ₀ 10, the CPU 2 finishes sending out the read instruction signal 37 that has been sent before, so the data on DATA ₀ 10 becomes invalid ( becomes logic “0”). In addition, the input/output device 6 recognizes that the CPU 2 has received data by detecting that the BSI ₁ 19 signal has ended, and transmits the previously sent data 39 and the response signal 4.
1 ends.

The above series of operations completes the data reading operation from the input/output device 6 by the CPU 2.

The above describes an example of a bus expansion method using a conventional _input / _output bus bus coupling circuit. )
The control of the transmission direction was performed using a part of the signals that constitute the input/output bus (corresponding to BSI ₀ 14 in FIG. 2). In the above-mentioned embodiment, this is done using the read instruction signal (BSI ₀ ) 14, but this signal determines the right to use the bus only by the CPU and is sent out asynchronously, so it is not suitable for multiprocessor systems, etc. If multiple CPUs are connected to different buses (for example, if a CPU is also connected to IOB ₀ 8 in Figure 1), the directionality of the bidirectional bus driver of the bus coupling circuit is not determined and it cannot be handled. There were flaws.

The present invention is intended to improve the above-mentioned drawbacks of the conventional technology, and its purpose is to provide a bus configuration system that allows any device to be connected to any position on any bus, and The device is equipped with a bus right determination circuit that sends a bus use permission signal to the corresponding device based on the bus use request signal from each device connected to the bus, and also uses the bus use permission signal to control the signals in the bus coupling circuit. It is characterized by determining the transmission direction.

Examples will be described below with reference to the drawings.

FIG. 4 shows an example of the system configuration in the first embodiment of the present invention, in which 50 to 51 are internal buses 0 (IBUS ₀ ) and 1 (IBUS ₁ ) used for information transmission between devices, and 52 ~53 is central processing unit 0
(CPU ₀ ) and central processing unit 1 (CPU ₁ ), 54-5
5 is main memory device 0 (MM ₀ ) and main memory device 1
(MM ₁ ), 56 to 57 are input/output device 0 (IO ₀ ) and input/output device 1 (IO ₁ ), 58 is IBUS ₀ 50 and IBUS ₁
Bus coupling circuit (BUS CUP) that couples 51, 5
9 receives a bus use request signal (BRQ) from each device, determines which device is allowed to use the bus according to a predetermined priority order, and sends a bus use permission signal (BAK) to that device. and a bus transmission direction control signal (BRIR) 72 for controlling the signal transmission direction within the BUS CPU 58.
The bus usage right determination circuit (BUS
ABT), 60 to 65 are BUS ABT59 from each device.
Bus use request signal (BRQ) sent to 66~
71 is a bus use permission signal (BAK) sent from the BUS ABT 59 to each device.

FIG. 5 shows an example of the circuit configuration of the bus coupling circuit (BUS CUP) 58 and the bus usage right determination circuit (BUS ABT) 59 in the first embodiment of the present invention.
80-84, 94-95 are inverter circuits, 85
90 is an AND gate, and 91 is a state indicating which of the plurality of buses IBUS ₀ and IBUS ₁ is permitted to use the buzz, that is, the state of the bus use permission signal BAK. It is an OR gate. Here, or gate 9
Only the bus use permission signal BAK for the device connected to IBUS ₀ is connected to IBUS 1, but when the output of OR gate 91 is “0”, the other
It is assumed that any device connected to IBUS1 is authorized to use the bus. Reference numerals 92 to 93 denote flip-flops (FF) that send out bus transmission direction control signals BDIR72 to 73, which are determined according to the state of the bus permission signal BAK.
The output of FF93 is input to the input terminal D of FF93, and the I-phase clock CLK() and phase clock are respectively input.
It is controlled by CLK(). Here, the I-phase clock CLK() is IBUS ₀ 50 or CBUS ₁ 5
It serves as a timing clock when each device connected to 1 sends data as a sending device,
The phase clock CLK() functions as a timing clock by which each of the devices, as a receiving device, sends a response back to IBUS ₀ 50 or CBUS ₁ 51. These phase clock CLK() and phase clock CLK
() has a fixed timing of occurrence,
They are generated from any one location within the information processing system so as to be generated at a constant timing and maintain a constant phase relationship with each other, and are commonly used in each device and each circuit. Furthermore, 96 to 99 are bus drivers for relaying bus information controlled by the respective outputs of flip-flops FF92 and 93, and output bus transmission direction control signals BDIR72 to 73 outputted from flip-flops FF92 and 93, respectively.
, phase clock CLK(), phase clock CLK
The directionality of the BUSCUP 58 is switched in synchronization with ().

FIG. 6 shows the timing relationship of control signals in the first embodiment of the present invention. FIG. 7 shows the contents transmitted on the bus in the first embodiment of the present invention.

Next, the operation in the first embodiment of the present invention will be explained in detail with reference to FIGS. 4 to 7. first, fourth
A case will be described in which the CPU ₀ 52 in the figure reads data from the MM ₁ 55. First, CPU ₀ 52 sends a bus usage request to BUS through CPU ₀ /BRQ60.
It is sent to the ABT 59 at the timing 110 in FIG. Incidentally, the bus use request signal BRQ of each device (the requesting device name is suffixed in the signal names in FIGS. 5 and 6) is sent out in synchronization with the phase clock. In BUS ABT59, CPU ₀ .
BRQ60 is connected to AND gate 89(5).
At this time, the devices with higher priority MM ₀ , MM ₁ ,
When there is no bus use request from either device IO ₀ or IO ₁ (bus use request signals 62 to 6 of each device
5 is all “0”) is an AND gate 8
9 other input lines 89-(1) to (4) are each connected to the inverter 8.
Logic “1” because it is connected to outputs 0 to 83
is input, and "1" is outputted to the bus use permission signal CPU0 _BAK66 , which is the output of the AND gate 89, as shown in FIG. 6 111. Further, the output of the AND gate 89 is connected to the input of the OR gate 91(3), and "1" is output to the output line of the OR gate 91 for giving "1", and this signal is the input signal of the input terminal D of the FF92. "1" is input as the value. In this state, when the phase clock is input to the clock terminal C of the FF 92, the FF 92 is set to "1" at timing 112 in FIG. Furthermore, the output terminal Q of FF92 is the input terminal D of FF93.
Since it is connected to , “1” is input. In this state, the phase clock is clock terminal C of FF93.
is input, at timing 113 in Figure 6
FF93 is set to "1".

On the other hand, CPU ₀ is CPU ₀・BAK of BUS ABT59
When the bus use permission signal 111 is received by the bus 66, the DATA information (information 150 to 155 in FIG. 7) is sent to the IBUS ₀ 50 at the timing 114 in FIG. 6 for one cycle from the next phase clock.
Send to. In this case, the DATA section 100 (FIG. 5) of the IBUS ₀ 50 contains memory address related information, the data flag 150 is set to "1" to indicate that the content on the DATA line is valid, and the receiving device specification 151 is set to "1". MM ₁ designation, transmitter designation 152
is a CPU ₀ designation, control information 153 is a read operation designation, address information 154 is a memory address designation in MM ₁ , and data information 155 is an arbitrary value (generally all zeros).

The above DATA information is the DATA line 100 in Figure 5.
The signal is transmitted to the relay bus driver 96 of the BUS CUP 58 via. (In Figure 5, only one driver is shown as a representative.) At this time, the output "1" signal of the FF92 mentioned above is output from driver 1.
The contents of the DATA line 100 of the IBUS ₀ are input to the control terminal C of the relay bus driver 96 through the signal line 72 via the IBUS 04.
It is sent to the DATA line 101 of IBUS ₁ . on the other hand,
The output of the FF 92 is connected to the control terminal C of the relay bus driver 97 through the driver 104 and the signal line 7.
After being transmitted via DATA line 10, the inverter circuit 95 inverts it to "0" and inputs it, so the relay bus driver 97 becomes invalid and the DATA line 10
1 information is not propagated to the DATA line 100.

The DATA information sent from CPU ₀ 52 according to the control contents described above is transmitted to IBUS ₀ 50 and IBUS ₁ 51.
It is transmitted to DATA lines 100 and 101. Next, the devices connected to IBUS ₀ 50 and IBUS ₁ 51 transmit information on the DATA line if the content of the receiving device designation information 151 sent out on the DATA line 100 or 101 specifies the own device. Other information 152 to 155 are input, and it is determined whether or not the operation specified by the control information 153 can be executed. In this case, it is generally determined whether there is a parity error, an in-operation order, an invalid order, etc. on the bus. In this embodiment, MM ₁ 55 performs the above series of operations.
That is, after receiving the action instruction, MM ₁ 55 performs the above judgment action, and then determines if the specified action is executable.
Information 152~ on the DATA line 101 with the phase clock
155 is set in an internal register (not shown), and the above judgment result is set as status information 157 together with a response flag 156 (="1") in synchronization with the phase clock at timing 115 in FIG. 6 in one cycle. It is sent to the RLY line 103 during the cycle.
Note that if the specified operation cannot be executed, only the above judgment result is used as the status information 157 and the response flag 15 is
6 and sent to the RLY line 103 in the same manner as above.

On the other hand, the control terminal C of the RLY line relay bus driver 98 (only one driver is shown in FIG. 5) of the BUS CUP 58 is connected to the BUS ABT
59 BDIR() FF93 output (at this time FF93
is set to "1" by the above operation. )
are connected via the buffer 105 and the signal line 73, the contents of the RLY line 103 are relayed to the RLY line 102 by the bus driver 98.
In addition, since the signal line 73 is connected to the control terminal C of the bus driver 99 via the inverter circuit 94, a "0" signal is inputted to the bus driver 99.
9 becomes invalid and the content of RLY line 102 is RLY
It is not relayed to line 103.

The response information (response flag, status information) sent from MM ₁ 55 by the above operation is transmitted to the RLY line 103,
It is transmitted to CPU ₀ 52 via bus driver 98 and RLY line 102. The CPU ₀ 52 can know from the response information whether the MM ₁ 55 has successfully received the DATA information and can start the specified operation.

Next, the MM ₁ 55, which has received the DATA information through the above operation, performs a read operation of the stored contents according to the control information 153 (read operation designation in this embodiment) and address information 154. MM ₁
55 reads the read data after the operation is completed.
Bus use request line to send to CP ₀ 52
A bus use request signal is sent to the BUS ABT 59 through the _MM1 /BRQ 63 at timing 116 in FIG. The above MM ₁ /BRQ63 is BUS
Since it is connected to the input terminal 2 of the AND gate 86 of ABT59, if a bus use request is not issued from MM ₀ 54 at this time, MM ₀ BRQ 6
2 is a "0" signal, and since the "1" signal is sent out by the inverter circuit 80 and input to the input terminal 1 of the AND gate 86, the AND gate 86
A “1” signal is output as the output of
It is transmitted to the MM ₁ 55 through the MM ₁ /BAK line 69 as a bus use permission signal at timing 117 in FIG. In this case, MM ₁ 55 is IBUS ₁ 51
Since the device is connected to the OR gate 91, the output of the AND gate 86 is not connected to the input terminal of the OR gate 91. In addition, since the input terminal 1 of the OR gate 91 is connected to the output of the AND gate 85, if a bus use request is not issued from MM ₀ 54, MM ₀ BRQ62 is "0", so the AND gate 85 The output of the OR gate 91 becomes "0", and the input signal of the input terminal 1 of the OR gate 91 becomes "0". On the other hand, the other input terminals 2 and 3 of the OR gate 91 are an AND gate 87 and an AND gate 89, respectively.
However, since the output of the inverter circuit 81 is connected to one input of the two AND gates 87 and 89, a "0" signal is input (at this time, the inverter circuit 81 Since the input of the AND gates 87 and 89 is a "1" signal, the outputs of the AND gates 87 and 89 become "0" signals. As a result of the above, all input signals of the OR gate 91 are “0”.
Because of the signal, the output of the OR gate 91 is “0”
Since the signal is output and becomes the input signal of BDIR()FF92, BDIR()FF92 is set to "0" when the next phase clock is input. (118 in Figure 6; the dashed line in the figure is “0”)
Indicates the condition. )BDIR()The output signal of FF92 is passed through the driver 104 and signal line 72.
Since this is the input to the control terminal C of the relay bus driver 96 in the BUS CUP 58, the bus driver 96 is in an invalid state and the contents of the DATA line 100 are
It is not relayed to the DATA line 101. On the other hand, the inverter circuit 9 is connected to the control terminal C of the bus driver 97.
5, the "1" signal is input as a negative signal of the output of the AND gate 104, and the bus driver 97 becomes valid and the DATA line 10
1 is set to be relayed to the DATA line 100. At this time, the above MM ₁・BAK signal 11
MM ₁ 55, which received 7, synchronizes the DATA information with the phase clock and synchronizes it with the timing 120 in Figure 6.
It is sent to the DATA line 101 for one cycle (until the next one-phase clock). DATA in this case
As information, the data flag 150 is “1”
The signal includes CPU ₀ designation as receiving device designation 151 (the contents of transmitting device designation information 152 that MM ₁ previously received from CPU ₀ is used), MM ₁ designation as transmitting device designation 152, and control information 153.
The operation result report is specified as address information 154.
The error information (if the operation was executed normally, all zeros are set, and if an error is detected during execution of the operation, the error content is set.)
Furthermore, read data is sent as data information 155.

Through the above-described operation, the DATA line 101 sent out from MM ₁ 55, the bus driver 97 of BUS CUP 58, and the DATA line 100 are routed.
It is transmitted to CPU ₀ 52. CPU ₀ 52 is the above
By detecting that CPU ₀ is designated in the receiving device designation information 151 on the DATA line 100, the next phase clock (Fig.
21 timing) Other DATA information 152-1
55 in the internal register, and also sends the status information 157 regarding the reception operation along with the response flag 156 to the RLY line 10 at timing 122 in FIG.
Send to 2. On the other hand, BDIR in BUS ABT59
() The input terminal D of FF93 is the above-mentioned BDIR ()
Since the "0" output signal of FF92 is input, BDIR()FF93 is set to "0" at the next phase clock. (Timing of 119 in Figure 6:
In the figure, the "0" state is indicated by a broken line. ) The BDIR
() The output of the FF93 is connected to the control terminal C of the bus driver 98 in the BUS CUP 58 via the driver 105 and the signal line 73, and the “0” signal is input, so the bus driver 98 is disabled and the RLY line The contents of 103 are not relayed to RLY line 102. Further, the output of the BDIR() FF93 is passed through the driver 105, the signal line 73, and the inverter circuit 94 to the control terminal C of the bus driver 99.
Since the bus driver 99 is connected to the control terminal C, a "1" signal is input to the control terminal C, and the bus driver 99 becomes valid, and is set to relay the contents of the RLY line 102 to the RLY line 103. Due to these operations, the status information 157 and response flag 156 sent from the CPU ₀ 52 are transferred to the RLY line 102 and the BUS
CUP58 bus driver 99 and RLY line 103
It is transmitted to MM ₁ 55 via.

Due to the above-mentioned series of operations, CPU ₀ 52
A read operation of memory data from MM ₁ 55 is performed. Note that in this embodiment, IBUS ₀
50 and IBUS ₁ connected to 51 different buses
Although the operation between CPU ₀ 52 and MM ₁ 55 has been described, data transfer between other types of devices is performed in a similar manner. In addition, the same bus (IBUS ₀ 5
0 or IBUS 51), the relay bus drivers 96 to 99 of the BUS CUP 58 are controlled by the series of operations of the BUS ABT 59 described above.
Only one device that has received a bus use permission signal sends data, and the other devices send a "0" signal (this is a general bus configuration method, so the explanation will be omitted). A "0" signal is relayed for data from buses other than those to which devices are connected. Therefore, data transfer between two devices connected within the same bus can be performed normally. 6th
Each signal timing shown in figure b is IO ₀ 56 is MM ₀
When transferring data to 54, CPU ₁ 5
The bus usage request from IO ₀ 56 and the bus usage request from IO 0 56 occur simultaneously, and the bus usage request from IO ₀ 56 is accepted preferentially by BUS ABT 59.
This shows a case where acceptance of a bus use request from CPU ₁ 53 is delayed by one cycle. In Figure 5
If IO ₀ /BRQ64 and CPU ₁ /BRQ61 are sent to BUS ABT59 at the same timing, IO _0/ BRQ64 is sent to the input terminal (3) of AND gate 90.
Since BRQ64 (“1” signal) is input through the inverter circuit 82, “0” signal is input and the output of AND gate 90 (CPU ₁ /BAK67) is “0”.
The bus usage request from CPU ₁ 53 is not accepted, and the bus usage request from IO _{0 56} is rejected.
It remains in a waiting state until the BRQ 64 becomes a "0" signal and is accepted in the next cycle (timing 123 in FIG. 7). Other operations are CPU ₀ as mentioned above
52 and MM ₁ 55.

Note that the bus use permission signal (BAK), which is not described in this embodiment, is not sent individually for each device, but is encoded and sent in the form of a device number, thereby reducing the number of bus use permission signal lines. can also be easily realized.

As explained above, in the first embodiment, individual bus request (BRQ) signals from each device are
A priority determination circuit (inverter circuits 80 to 84, AND gate 8
5 to 90), and the bus use permission signal (BAK) is determined by the individual bus use permission signal lines 66 to 71.
Based on the bus use permission signal, BUS CUP is sent to the bus use permission device according to the bus position to which the use permission device is connected.
The relay direction of the relay bus drivers 96 to 99 of 58 is determined by the bus driver control signal BDIR() 72,
Because it is controlled by BDIR()73, data can be transferred between any devices connected to any bus location, regardless of the type of device, without the need to newly provide a special signal to control the bus coupling circuit. There is an advantage in being able to do this.

In the first embodiment, data transfer between devices was explained, but as shown in FIG.
Processing system (CP) 16 consisting of IO etc.
0 to 163 to common bus 0 (CBUS ₀ ) 164 and common bus 1 (CBUS ₁ ) 165 via common bus adapters (CBADP) 166 to 169 to realize bus expansion in a multiprocessor system. Can be done. That is, data transfer between CPs or CP and common main memory (CMM ₀ ,
1) When transferring data with the common input/output devices (CIO ₀ , 1), a bus request signal is sent from the CBADP of each CP via the bus request line (BRQ) as in the first embodiment. and send it to BUS ABT170,
After receiving the bus permission signal from the BUS ABT170 via the bus permission signal line (BAK), by sending the necessary data to the common bus,
BUS ABT170, BUS CUP171, CBUS ₀
164, CBUS ₁ 165 is the first embodiment (however,
IBUS in the first embodiment is CBUS. ), data can be transferred between any devices.

In a multiprocessor system like this example, the number of devices that make up the system increases;
As the mounting space and devices connected to each bus become larger, it becomes difficult to satisfy the electrical conditions of the bus (bus length, number of loads connected to the bus, etc.), and the types of devices connected to each bus also increase. do.

However, by expanding the common bus using the present invention, the electrical conditions for the bus, which is the problem mentioned above, can be improved, and any type of device or system can be connected to any bus location. arise.

In the first and second embodiments, one BUS
This is an example of connecting two sets of buses using a CUP, but by providing two or more BUS CUPs as shown in Figure 9 (Figure 9 only shows the case of two), the number of buses can be reduced to three. It is also possible to increase the number more than that.

In this case, prepare two sets of bus direction control circuits (BDIR FF92, 93, drivers 104, 105) for BUS ABT59 shown in Fig. 5, and set BUS CUP ₀ ,
Create a control signal for the relay bus driver for BUS CUP ₁ . First, a bus use permission signal (BAK: not shown) for devices 181, 182, etc. connected to BUS ₀ 180 is input to an OR gate (not shown: equivalent to 91 in FIG. 5), and the output of the OR gate is sent to BUS CUP. ₀ This is the input signal for the bus direction control circuit for 183 control. Then BUS ₀ 180 and BUS ₁
Devices 181, 182, 18 connected to 185
The bus use permission signal for BUS CUP 1, 187, etc. is input to an OR gate (not shown) in the same way as described above, and the output of the OR gate is used as an input signal to the bus direction control circuit for controlling BUS CUP ₁ 184. Also, BUS
The configurations of CUP ₀ 183 and BUS CUP ₁ 184 are the same as the BUS CUP 58 in FIG.

Now, when sending data from the device 181 or 182 connected to BUS ₀ 180, BUS ABT
When a bus use permission signal is sent from 191 to the bus use requesting device 181 or 182, the configuration of the OR gate and bus direction control circuit allows
Bus driver control signal (BDIR(), ()) 192 to BUS CUP ₀ 183 and BUS CUP ₁ 184
“1” is sent to 195 (timing is 6th
According to the diagram. ), for the DATA line, BDIR()1
BUS CUP ₀ by 92,194 BUS ₀ by 183
180 contents to BUS ₁ 185, and BUS CUP ₁
At 184, a bus driver (not shown) is configured to relay the contents of BUS ₁ 185 to BUS ₂ 188. Therefore, data sent from the device connected to BUS ₀ 180 is transferred from BUS ₀ 180 → BUS
CUP ₀ 183→BUS ₁ 185→BUS CUP ₁ 184
→It is sent to all devices in the system via the BUS ₂ 188 route. Furthermore, BDIR()193,
195, the RLY line is BUS CUP ₀ 183
Transfer the contents of BUS ₁ 185 to BUS ₀ 180 and
CUP ₁ 184 changes the contents of BUS ₂ 188 to BUS ₁ 18
Bus driver (not shown) to relay to 5
is set. Therefore, the response information from the receiving device can be received by the device connected to BUS ₀ 180 via the route in the opposite direction.

On the other hand, when data is sent from a device connected to BUS ₂ 188, the bus driver control signals 192 to 195 from BUS ABT 191 are all "0" signals due to the configuration of the bus direction control circuit described above.
Since the _{data is sent to BUS CUP183 and 184, the reverse route setting is performed when sending data from the device connected to BUS 0 180} mentioned above. It becomes possible to transfer data to other devices.

Next, when data is sent from a device connected to BUS ₁ 185, a "1" signal is sent only to the bus driver control signals 194 and 195 for BUS CUP ₁ 184 due to the configuration of the bus direction control circuit described above. Therefore, the DATA line is BUS CUP ₀ 1
In 83, the contents of BUS ₁ 185 are changed to BUS ₀ 18
0, and at BUS CUP ₁ 184 BUS ₁ 18
5 is set to be relayed to BUS ₂ 188. On the other hand, on the RLY line, the contents of BUS ₀ 180 are
to BUS ₁ 185, and the contents of BUS ₂ 188 to BUS ₁
185. Therefore,
Data transfer from a device connected to BUS ₁ to any other device is also possible.

As shown in this example, BUS CUP and BUS
By increasing the number of bus direction control circuits in the ABT, it is possible to combine three or more sets of buses to realize a large-scale system bus without requiring a complicated circuit configuration.

The present invention recognizes the connection position of a device connected to a bus based on a bus use request signal sent individually from the device, and creates a control signal for a relay bus driver of a bus coupling circuit based on a bus use permission signal. It can be used for bus control in large-scale systems that require multiple buses without providing any special signals. Furthermore, bus expansion is extremely easy.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram in a conventional embodiment, FIG. 2 is a configuration diagram of a bus coupling circuit in a conventional embodiment, FIG. 3 a and b are time charts of control signals in a conventional embodiment, and FIG. The figure is a system configuration diagram of the first embodiment of the present invention, and FIG.
A configuration diagram of a bus coupling circuit (BUS CUP) and a bus usage right determining circuit (BUS ABT) in an embodiment of
FIG. 6 is a time chart of control signals in the first embodiment, FIG. 7 is a diagram of information content sent from the device to the bus in the first embodiment, and FIG. 8 is a diagram of the second embodiment of the present invention. FIG. 9 is a system configuration diagram of a third embodiment of the present invention. 50, 51... Internal bus, 52, 53... Central processing unit, 54, 55... Main storage device, 56, 57... Input/output device, 58... Bus coupling circuit, 59... Bus usage right determining circuit.

Claims (1)

[Claims] 1 A plurality of bidirectional buses are coupled by a bus coupling circuit, and each bidirectional bus is connected to at least one device group consisting of a central processing unit, a main storage device, and an input/output device, and the bidirectional buses and the bus In an information processing system that transmits and receives data between the respective devices via a coupling circuit, a bus usage right determining circuit that determines the priority order of each device regarding bus use and the directionality of the bus coupling circuit is provided for each of the devices. When transmitting data, each device sends a bus usage request signal to the bus usage right determining circuit, and the bus usage right determining circuit follows the predetermined priority of each device. Then, the bus use permission determination circuit sends a bus use permission signal to the device with the highest priority among the devices that sent the bus use request signal, and the bus use right determination circuit
Data from a sending device to a receiving device is sent from the bidirectional bus to which the sending device is connected to another bidirectional bus, and responses from the receiving device to the sending device are sent by the sending device. The bus coupling circuit is configured to generate a signal for switching the directionality of the bus coupling circuit based on the bus use permission signal so that the direction of data is returned from another bidirectional bus to the connected bidirectional bus. A bus configuration method characterized by exchanging data between devices on a bidirectional bus.