KR20050067324A - Interface device between master/slave devices and method thereof - Google Patents

Abstract

The present invention relates to an interface device between a master / slave device and a method thereof.

In the present invention, when the first master / slave device generates a transaction to access the slave function in the second master / slave device using the master function, the first master / slave device goes to the second master / slave device. Temporarily store the data to be sent in the request output buffer. Upon receiving an input enable signal through a control output multiplexer, data stored in the request output buffer is transmitted to the second master / slave device through the control output multiplexer and an address / data output multiplexer. Accordingly, the second master / slave device receives output data of the first master / slave device through a request input buffer, generates response data corresponding to the received output data, and temporarily stores the response data in the response output buffer. Thereafter, when receiving an input enable signal from the first master / slave device, the response data stored in the response output buffer is transmitted to the first master / slave device. According to this invention, deadlock is prevented and clock speed compensation is possible.

Description

Interface device between master / slave devices and method

The present invention relates to an interface device and a method between devices, and more particularly, to an interface device and a method between a plurality of master / slave devices having both a master function and a slave function.

In general, a bus of a system on chip has a master interface or a slave interface according to the type of devices included in the chip, and a separate bus for selecting a master interface. It has an arbiter and a separate bridge type device (ie clock speed compensation circuit) to compensate for clock speed. The conventional system-on-chip has an interface as described above and separates the address and control buses to compensate for the high-speed clock operation inside the chip, and separates the data input / output buses. This bus structure applies to both master and slave devices.

Recently developed devices are generally developed to have both master and slave functions according to the intelligence of the device, and also have a direct memory access (DMA) controller in the case of having an external bus interface such as a Peripheral Component Interconnect (PCI). As functions are built into the device, it is a common device trend to have both master and slave functions.

Hereinafter, an operation of an interface between a device having a conventional master and a slave function will be described with reference to FIG. 1. 1 is a block diagram illustrating a partial configuration of a system on a chip interface according to the prior art.

As shown in FIG. 1, the system on chip includes a first device 10, a second device 20, and an Nth device 30, and includes a first device 10, a second device 20, and a first device 10. N device 30 has both a master device and a slave device.

Herein, when the master device 11 of the first device 10 wants to access the slave device 22 of the second device 20, the master device 11 may use the bus arbiter 70. The bus transaction is started after receiving a bus permission signal from the bus arbiter 70. At this time, the bus arbiter 70 receiving the bus use request from the master device 11 instructs the master data output multiplexer 40 and the master control output multiplexer 50 to use the bus of the master device 11. The master data output multiplexer 40 and the master address / control output multiplexer 50 instructed to use the bus from the bus arbiter 70 receive the data and address / control signals from the master device 11, and the slave device 22. Send to the side.

The slave device 22 which decodes the corresponding control input transmits a response signal and data to the slave data output multiplexer 60, and the slave data output multiplexer 60 of the slave device 22 outputting data. A path for transmitting the data value to the master device 11 is formed.

As a result, a request and a response to one transaction are made through the above-described method, while the use of the other master devices 21 and 31 and the slave devices 12 and 32 is prohibited.

However, in order for a device to have both a master and a slave interface for the above-described conventional interface method, it is necessary to accommodate both a data bus having separate input and output addresses and control signals. This requires a very large number of signal lines, and because it uses a synchronous method is impossible clock speed compensation on the interface, there is a problem to have a separate clock speed compensation circuit inside the device.

In addition, when one master device and a slave device are in use, other master and slave devices cannot be used, so a deadlock may occur due to a response delay. In order to prevent such deadlock, a very complicated arbitration algorithm is required.

In the prior art, there is no consideration of the transaction separation scheme employed in PCI-X or PCI Express, and thus it is impossible to process the request or response packets inside the interface when they are intermingled with each other. To solve this problem, consideration should be given to the order of transactions through the addition of complex algorithms or circuits inside the chip, which leads to an increase in the internal buffer size of the chip, thereby reducing the overall efficiency of resource usage within the chip. And there is a problem that complicates the chip configuration.

Accordingly, an aspect of the present invention is to solve the conventional problems, and to provide an interface device and a method having both a master and a slave interface and minimizing a signal line while considering a transaction separation method.

Another object of the present invention is to provide an interface device and a method for enabling such clock speed compensation by using a buffer on an interface when the operating speed of the device is different.

According to an aspect of an exemplary embodiment of the present invention, an interface device between a plurality of master / slave devices having both a master function and a slave function may include: outputting a plurality of control outputs between the plurality of master / slave devices; A control output multiplexer for transmitting to a corresponding destination master / slave device among the master / slave devices of the controller; An address / data output multiplexer which receives the address / data output of the plurality of master / slave devices and the response signal of the address / data output and transmits to the corresponding destination master / slave device among the plurality of master / slave devices; Each of the plurality of master / slave devices separates a control signal and an address / data output for one transaction and outputs the control output multiplexer and the address / data output multiplexer, and each of the plurality of master / slave devices is a transmission destination. Transmit the corresponding output when an input capable signal from the master / slave device is received.

In addition, the interface method according to another aspect of the present invention, if the first master / slave device generates a transaction to access the slave function in the second master / slave device using a master function, the first master / slave device; A slave device temporarily storing data to be transmitted to the second master / slave device in a request output buffer; A second step of determining, by the first master / slave device, whether an input capable signal transmitted from the second master / slave device is received through the control output multiplexer; The first master / slave device transmits data stored in the request output buffer to the second master / slave device through the control output multiplexer and the address / data output multiplexer when the input enable signal is received; ; A fourth step of receiving, by the second master / slave device, output data of the first master / slave device through a request input buffer; A fifth step of generating, by the second master / slave device, response data corresponding to the received output data and temporarily storing the response data in a response output buffer; And a sixth step of transmitting, by the second master / slave device, response data stored in the response output buffer to the first master / slave device when receiving the input enable signal from the first master / slave device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

2 is a block diagram of an interface device according to an embodiment of the present invention.

A device applied to an embodiment of the present invention is a master / slave device having a master device and a slave device as shown in FIG. 1. 2 is a form that can be easily implemented by those skilled in the art, and includes four master / slave devices, that is, a first master / slave device 100, a second master / slave device 200, and a first embodiment. 3 describes how the interface between the master / slave device 300 and the fourth master / slave device 400 is achieved.

As shown in FIG. 2, the interface apparatus according to an exemplary embodiment of the present invention provides a control output multiplexer for controlling the transfer of control signals input and output between a plurality of master / slave devices 100 to 400 and a master / slave device. And an address / data output multiplexer 600 for controlling the transfer of address / data signals input and output between the master / slave devices.

Hereinafter, a process in which the first master / slave device 100 accesses a slave function in the second master / slave device 200 using the master function will be described.

The control output multiplexer 500 stores the availability information received from the second master / slave device 200 and then enables the master / slave device 200 to be used by the first master / slave device 100. Tell whether or not.

Accordingly, when the first master / slave device 100 knows that it can be used, it sends its control signal to the control output multiplexer 500 and also sends the address / data signal to the address / data output multiplexer 600. Send to. Then, the control output multiplexer 500 and the address / data output multiplexer 600 send the received signal to the second master / slave device 200.

The second master / slave device 200 interprets the received control signal to know that it is selected and generates a response signal inside the device. Here, even before the second master / slave device 200 generates the response signal, the first master / slave device 100 may further generate a request signal, so that the transaction separation scheme may be faithfully used. When the first master / slave device 100 has an external interface that is in a transaction separation method, deadlock does not occur in the interface according to the present invention even if the request packet and the response packet are mixed with each other from the outside.

When the second master / slave device 200 receives the response receivable signal of the first master / slave device 100 from the control output multiplexer 500 in a state where the response and the data are prepared, the second master / slave device 200 receives the response state and the data. Transmit to the address / data output multiplexer 600 and the control output multiplexer 500 to be transmitted to the first master / slave device 100.

FIG. 3 is a block diagram illustrating the structure and connection of each device for explaining how an interface between two devices operating as described above is made. As shown in FIG. 3, the interface device of the present invention includes a master / slave device 100, 200, a control output multiplexer 500, and an address / data output multiplexer 600.

Each of the master / slave devices 100 and 200 has a request output buffer, a request input buffer, a response input buffer, and a response output buffer, wherein the request output buffer and the response input buffer have a transaction generation block 110 for generating a transaction. 220, the request input buffer and the response output buffer form a transaction processing block (120, 210) for processing a transaction.

The control output multiplexer 500 consists of an output multiplexer and an input demultiplexer, which are included in each master / slave device 100, 200, respectively. The address / data output multiplexer 600 is composed of an output multiplexer and an input demultiplexer, and the output multiplexer and the input demultiplexer are included in the respective master / slave devices 100 and 200, respectively.

In FIG. 3, for convenience of understanding, the output multiplexer of the control output multiplexer 500 and the address / data output multiplexer 600 for each master / slave device is treated as a single block 720 and 730, and the control output multiplexer. The input demultiplexer of the 500 and the address / data output multiplexer 600 are processed as one block 710 and 740 for each master / slave device.

So look at the behavior, I). When the master / slave device 100 receives the request input enable signal of the master / slave device 200 from the output multiplexer 720, when the address and control data are prepared in the request output buffer 111, the request signal and Send data to output multiplexer 720.

II). When the output multiplexer 720 receives the request signal from the request output buffer 111, it generates an appropriate control signal and sends it to the input demultiplexer 740 of the master / slave device 200, and the input demultiplexer 740. ) Examines a control signal called a chip select signal and a request signal received from the master / slave device 100 and transmits it to the request input buffer 211.

III). The master / slave device 200 processes the request inside the device with the signal received by the request input buffer 211 and stores it in the response output buffer 212.

Here, the master / slave device 200 generates the request signal in the request output buffer 212 even during the processing time and transmits the process S305 to the master / slave device 100 through the output multiplexer 730. The response output buffer 122 of the master / slave device 100 may operate to send the stored information to the master / slave device 200 through the output multiplexer 720. Since this process can be performed without any limitation, according to the above description, it can be seen that no deadlock occurs in the interface device and method of the present invention.

IV). The master / slave device 200 prepares the response status and data for the signal requested by the master / slave device 100 in the response output buffer 212 and, when ready, transmits the master / slave device from the response input buffer 112. After detecting the response input enable signal of 100, the prepared data is transmitted to the input demultiplexer 710 of the master / slave device 100 through the output multiplexer 730.

V). The input demultiplexer 710 stores the response received from the response output buffer 212 in the response input buffer 112.

VI). Accordingly, the transaction connecting from the master / slave device 100 to the master / slave device 200 is completed.

In the present invention, since the clocks of the read and write operations of the buffer inside the device can be different from each other, there is no restriction in data transfer even in a device having a different clock speed, and a separate clock compensation circuit is not required. In addition, since the bus structure used in the request output signal and the response output signal is shared, the signal line can be reduced in half, and since the address is structured to share the address bus and the data bus using only the first time, the signal line can be further reduced. have.

According to the above description, the present invention is structured to generate a chip select signal in the device itself, it is possible to select a device without a separate arbiter, in particular, in the case of connecting only two devices as shown in Figure 3 signal line This becomes simpler.

4 is a timing diagram in a signal line between two devices shown in FIG. As shown in FIG. 4, the master / slave device 100 examines the Reqin_rdy_i 1411 signal output from the master / slave device 200 and when the Reqin_rdy_i 1411 signal is 1, AddrData_o 1412 and Control_o ( 1413), the address data and the chip selection and control signals are outputted through the ChipSelect_o (1414) signal, and at this time, the write strobe signal and the data output end signal as the AddrCtrl_wr_o (1415) signal, the ReqData_wr_o (1416) signal, and the Data_wr_end_o (1417) signal. Outputs

In the above description, the Reqin_rdy_i 1411 signal is a request input enable signal transmitted from the master / slave device 200 to the master / slave device 100. The AddrData_o 1412 signal is an address data signal, the Control_o 1413 signal is a control signal, and the ChipSelect_o 1414 signal is a chip select signal. The AddrCtrl_wr_o 1415 signal and the ReqData_wr_o 1416 signal are write strobe signals, which are address / control write strobe signals informing the address and data area, and request data write strobe signals. The Data_wr_end_o 1417 signal is a signal indicating the end of data.

The response data prepared by the slave device of the master / slave device 200 that received the data is checked for AddrData_i (1422) and Control_i (1423) after checking the Cplin_rdy_o (1421) signal output from the master device of the master / slave device (100). Signal is input to the master / slave device 100, and at this time, a write strobe and a data end signal including the CplStatus_wr_i 1424, CplData_wr_i 1425, and Data_wr_end_i 1426 signals are also input. Thus, one bus transaction is terminated in the manner described above.

The Cplin_rdy_o 1421 signal is a signal transmitted from the master / slave device 100 to the master / slave device 200 and informs the transmission timing of the response data. The AddrData_i 1422 and Control_i 1423 signals are signals transmitted from the master / slave device 200 to the master / slave device 100 and carry signals corresponding to the data. The CplStatus_wr_i 1424, CplData_wr_i 1425, and Data_wr_end_i 1426 signals are write strobe signals transmitted from the master / slave device 200.

At this time, the signal line knows whether the input is possible and uses the data and data write strobe signal on the output side. Therefore, even if this interface is used where the signal cannot guarantee timing, such as between the chip and the chip, the input signal is latched and the output signal is used. It can also be used by latching in the receiving device, which ensures stable data transmission and reception.

5 is a diagram illustrating control signal and response signal bit allocation used in FIG. 3.

The control signal output from the master / slave device 800 is composed of a command type, a command / data characteristic, an identification number, and a data length, and has a separate signal line. In addition, since the control signal includes the data length, each device can check whether there is an error in the data length by comparing the amount of data actually input with the value specified in the data length, and whether the CRC (Cyclic Redundancy Check) is checked in the command characteristics. If you add a CRC when you add and output data, you can also perform a CRC check.

Since the response signal of the master / slave device 900 is composed of response type, response status, remaining data start address, and remaining data length, the response data can be divided into several parts and sent according to the device internal status. Can be adjusted.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, according to the present invention, it is possible to prevent the deadlock in the interface between the devices having a transaction separation scheme externally. In addition, since each device has both master and slave functions, it can be used to interface between intelligent devices.

In addition, the present invention significantly reduces the signal lines even in the connection between the number of signal lines and devices that are sensitive to signal stability, and since the signal flow rules are stabilized, an easier interface is possible.

In addition, since the clock compensation circuit is included in the interface circuit, the present invention enables a connection between a high speed device and a low speed device, and includes an instruction information in a control signal, thereby detecting errors in data transmission and reception. It allows you to.

In addition, the present invention allows the interface between devices without the need for a separate complex arbiter by embedding a chip select signal inside the interface signal.

1 is a block diagram illustrating a partial configuration of a system on a chip interface according to the prior art.

2 is a structural diagram of an interface device according to the present invention.

3 is a diagram illustrating a detailed interface between two devices shown in FIG. 2.

4 is a timing diagram in a signal line between two devices shown in FIG.

FIG. 5 is a diagram illustrating control signal and response signal bit allocation used in FIG. 3.

Claims (12)

In the interface device between a plurality of master / slave devices having both a master function and a slave function, A control output multiplexer for transmitting a control output between the plurality of master / slave devices to a corresponding destination master / slave device among the plurality of master / slave devices; An address / data output multiplexer which receives the address / data output of the plurality of master / slave devices and the response signal of the address / data output and transmits to the corresponding destination master / slave device among the plurality of master / slave devices; Each of the plurality of master / slave devices separates a control signal and an address / data output for one transaction, outputs the control signals to the control output multiplexer and the address / data output multiplexer, and transmits them from a transmission destination master / slave device. The interface device, characterized in that for transmitting a corresponding output when a signal is received. The method of claim 1 Each master / slave device A plurality of request output buffers for temporarily storing control outputs and address / data outputs generated when a transaction occurs, and a response input buffer for receiving and temporarily storing a response of a destination master / slave device to the output of the request output buffers. A transaction generator; A plurality of request input buffers for temporarily storing the control and address / data outputs received according to a transaction occurring at the opposite master / slave device, and a response output buffer for temporarily storing a response to the signal received in the request input buffer. Transaction processing unit Interface device comprising a. The method of claim 1 The control output multiplexer consists of an output multiplexer and an input demultiplexer, wherein the output multiplexer and the input demultiplexer are respectively present in each master / slave device, and the output multiplexer outputs the output of the device that has made a transaction to the input demultiplexer of the destination device. And transmitting to a multiplexer, wherein the input demultiplexer receives the output transmitted from the output multiplexer and transmits the output to its own device. The method of claim 3, The address / data output multiplexer consists of an output multiplexer and an input demultiplexer, wherein the output multiplexer and the input demultiplexer are respectively present in each master / slave device, and the output multiplexer outputs the output of the device that generated the transaction to the destination device. Transmitting to the input demultiplexer, wherein the input demultiplexer receives the output transmitted from the output multiplexer. The method of claim 4, wherein Every master / slave device broadcasts the input enable signal indicating whether it is available to the other master / slave device through the control output multiplexer when another master / slave device is accessible to itself. Interface device. The method of claim 5, Every master / slave device includes a data write strobe signal when transmitting data to another master / slave device, and the signal includes a command type, a command / data characteristic, an identification number, and data length information. The method of claim 6 And the response signal transmitted from the master / slave device includes response type, response status, remaining data start address, and remaining data length information. A plurality of master / slave devices having both a master function and a slave function; a control output multiplexer for relaying control outputs between the plurality of master / slave devices; and an address for relaying addresses / data outputs between the plurality of master / slave devices. An interface method between a master / slave device in an apparatus comprising a data / data output multiplexer, If the first master / slave device issues a transaction to access the slave function on the second master / slave device using the master function, a) the first master / slave device temporarily storing data to be sent to the second master / slave device in a request output buffer; b) the first master / slave device determining whether an input capable signal transmitted from the second master / slave device is received through the control output multiplexer; c) the first master / slave device sending data stored in the request output buffer to the second master / slave device through the control output multiplexer and the address / data output multiplexer when the input enable signal is received; ; d) the second master / slave device receiving output data of the first master / slave device through a request input buffer; e) generating, by the second master / slave device, response data corresponding to the received output data and temporarily storing the response data in a response output buffer; And f) when the second master / slave device receives an input enable signal from the first master / slave device, transmitting response data stored in the response output buffer to the first master / slave device; Interface method comprising a. The method of claim 8 In step b), if the first and second master / slave devices are in a state where other master / slave devices can access the device, the first and second master / slave devices may send all other masters through the control output multiplexer to the input enable signal indicating whether they are available. Interface method for transmitting to / slave device. The method of claim 8, Every master / slave device includes a data write strobe signal when transmitting data to another master / slave device, and includes the command type, command / data characteristics, identification number, and data length information. The method of claim 10, The master / slave device receiving the data strobe signal further comprises comparing the stored data length with the data length included in the signal and checking whether there is a data error. The method of claim 10, If the signal includes CRC check information, the master / slave device further comprises performing a CRC check.