JPH0410775B2 - - Google Patents
Info
- Publication number
- JPH0410775B2 JPH0410775B2 JP57213974A JP21397482A JPH0410775B2 JP H0410775 B2 JPH0410775 B2 JP H0410775B2 JP 57213974 A JP57213974 A JP 57213974A JP 21397482 A JP21397482 A JP 21397482A JP H0410775 B2 JPH0410775 B2 JP H0410775B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- receiving
- buffer memory
- transmitting device
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 54
- 230000015654 memory Effects 0.000 claims description 36
- 238000012546 transfer Methods 0.000 claims description 34
- 239000000872 buffer Substances 0.000 claims description 26
- 238000011960 computer-aided design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000013307 optical fiber Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Description
本発明はデータ伝送装置に係る。
CAD（Computer Aided Design）システム等
では、第１図に示すようなCPU（装置Ａ）と端末
の図面出力装置（装置Ｂ）間は従来並列信号線接
続されたハンドシエークによりデータ伝送が行な
われており、このようなCPUと端末機間の距離
は一般に数十ないし数百ｍ程度であつた。所が最
近は中央のCPU装置を中心に工場の各所端末が
CADやCAM（Computer Aided
Manufacturing）を実施しようとするとCPUと
端末の距離が数Kmから十数Kmに及ぶことになる。
このため、第１図に示したようなCPUと端末機
との間を第２図に示すようなデータ伝送回路で連
結したシステムが考えられるが、第２図に示した
ようなシステムでは最大データ転送速度が距離と
ともに減少してしまう欠点がある。即ち、第１図
に示す直結方式の場合のデータ転送のタイムチヤ
ートを第３図に示す。第３図に示すように装置Ａ
は装置Ｂが読込可能（RRDYがLowレベル）か
どうかを調べ、可能であればデータ転送を開始
（READをLowレベル）とする。この装置Ａのデ
ータ転送開始時点をt1とする。t1から装置Ｂの個
有の時間をおいてt2に装置Ｂは読込中即ち読込不
可を発信し、つづいて装置Ａはt3でデータ転送を
止め、装置Ｂはt4で再び読込可能に復帰する。装
置Ａは装置Ｂの読取可能を検出しt5で再びデータ
転送を開始し、以下同様に装置Ａ，Ｂ間でデータ
転送が行なわれる。ところが第２図に示すように
長さＬなる伝送線路が挿入されると装置Ａ，Ｂ間
の伝送線路を状態確認のための信号が往復するた
め最大データ転送速度が距離とともに減少する。
第２図に示す場合のデータ転送のタイムチヤー
トを第４図に示す。装置Ａは装置Ｂが読込可能
（RRDYがOFFレベル）かどうかを調べ、可能で
あればデータ転送を開始（READをOFFレベル）
とする。この時点をt11とする。転送データを伝
送線路を伝送遅れt0L（ここにt0は信号の伝送線路
単位長の伝搬時間）を伴つて伝搬し、装置Ｂは時
点t12からデータ取込を開始する。つづいて装置
Ｂは時点t13にデータ取込中（RRDYをONし）を
発信し、つづいて時点t14にデータ読込可能
（RRDYをOFFする）に戻る。この信号も伝送路
を所定の時間遅れt0Lを伴つて装置Ａに通知され
る。装置Ａは装置Ｂが取込開始を知つた上でt16
にデータ転送を止め、t17の時点で装置Ｂのデー
タ読込可能を知つた上で、t18の時点で再びデー
タ転送を開始する。第４図のタイムチヤートから
明らかな如くデータの伝送線路によるステイタス
確認信号の伝送遅れのためデータ最大転送速度は
大巾に遅れる。
第１表に最大データ転送速度と伝送線路長との
関係を示す。表中kw／ｓはキロワード／秒であ
り、伝送遅れは5μsec／Kmとする。
The present invention relates to a data transmission device. In CAD (Computer Aided Design) systems, data is conventionally transmitted between the CPU (device A) and the terminal's drawing output device (device B) by handshaking using parallel signal lines, as shown in Figure 1. The distance between such a CPU and a terminal device was generally several tens to several hundred meters. However, recently, terminals in various parts of the factory center around the central CPU unit.
CAD and CAM (Computer Aided
Manufacturing), the distance between the CPU and the terminal will range from several kilometers to more than ten kilometers.
For this reason, a system in which the CPU and the terminal shown in Figure 1 are connected by a data transmission circuit as shown in Figure 2 can be considered, but in the system shown in Figure 2, the maximum data The disadvantage is that the transfer speed decreases with distance. That is, FIG. 3 shows a time chart of data transfer in the case of the direct connection method shown in FIG. As shown in Figure 3, the device A
checks whether device B can read data (RRDY is at low level), and if possible, starts data transfer (READ is at low level). Let the data transfer start time of this device A be t1 . At t 2 after a time interval of device B's own time from t 1 , device B sends a message indicating that it is reading or cannot read, then device A stops data transfer at t 3 , and device B is able to read again at t 4 . to return to. Device A detects that device B is ready for reading and starts data transfer again at t5 , and data transfer is performed between devices A and B in the same manner thereafter. However, as shown in FIG. 2, when a transmission line of length L is inserted, a signal for checking the status travels back and forth on the transmission line between devices A and B, so the maximum data transfer rate decreases with distance. A time chart of data transfer in the case shown in FIG. 2 is shown in FIG. Device A checks whether device B can read data (RRDY is at OFF level), and if possible, starts data transfer (READ is at OFF level).
shall be. This time point is defined as t11 . The transfer data propagates through the transmission line with a transmission delay t 0 L (here, t 0 is the propagation time of the unit length of the signal transmission line), and device B starts acquiring data from time t 12 . Next, at time t13 , device B issues a message indicating that data is being taken in (turns RRDY ON), and then returns to enable data reading (turns RRDY OFF) at time t14 . This signal is also notified to device A along the transmission path with a predetermined time delay t 0 L. After device A knows that device B has started importing, it starts t 16
The device B stops data transfer at t17 , learns that data can be read from device B at t17, and starts data transfer again at t18 . As is clear from the time chart in FIG. 4, the maximum data transfer rate is significantly delayed due to the transmission delay of the status confirmation signal due to the data transmission line. Table 1 shows the relationship between maximum data transfer rate and transmission line length. In the table, kw/s is kiloword/second, and the transmission delay is assumed to be 5 μsec/Km.
【表】
本発明は送信側装置と受信側装置間をデータ伝
送線路で結ばれたことによるデータ転送の遅れを
解消したデータ伝送装置を提供することを目的と
する。
かかる目的を達成した本発明によるデータ伝送
装置の構成は、データ伝送が行なわれる送信側装
置と受信側装置と、上記送信側装置並びに受信側
装置を結ぶ長さＬなる伝送線路とからなり、上記
受信側装置にバツフアメモリを設け、該バツフア
メモリの中、受信側装置の使用中のメモリが特定
数N1を超えたときに上記受信側装置は上記送信
側装置にデータ転送停止の信号を送り、使用中の
メモリが特定数N2を切つたときは上記受信側装
置は上記送信側装置に対してデータ転送開始の信
号を送ることを特徴とするものである。
但し、前記バツフアメモリ数Ｎ、特定数N1、
N2の間には、下記の関係がある。
Ｎ≧Na＋２×ToL／Te
N1＞N2
Ｎ−N1＞２×ToL／Te
N2＞２ToL／Te
ここに、
Na：使用中のバツフア数、
To：伝送線路の単位長当りの伝搬時間、
Te：単位メモリの転送時間、
である。
上述の構成とすることにより、データ転送停止
の信号送信と、データ転送開始の信号送信との間
に、特定数N1とN2で定まるヒステリシスを与
え、伝送線路の長さＬもバツフアの一部として使
用することになり、バツフアメモリを最小限度に
することができる。
本発明によるデータ伝送装置の一つの実施例を
図面に従つて説明する。
第５図は本発明によるデータ伝送装置の一つの
実施例の構成図を示す。第５図においてＡは
CPU等のデータを発信する装置、１は装置Ａに
並列信号線で結ばれた送信側伝送装置、２は図面
出力装置等の端末装置Ｂに並列信号線で結ばれた
受信側伝送装置、３は送受信伝送装置を結ぶ長さ
Ｌなる光フアイバ等の伝送線路、４は受信側伝送
装置２内に設けられたバツフアメモリである。第
４図において、装置Ａのデータは第２図に示した
場合の如くデータ転送に際しいちいち受信側装置
の読込可能性を調べるものとは異なり、受信側伝
送装置２中にバツフアメモリ４を設け、端末装置
Ｂはバツフアメモリ４中に蓄えられた装置Ａから
転送されて来たメモリを逐次使用し、バツフアメ
モリ中の使用メモリ数が下限値N2を切ると端末
装置Ｂからデータ転送開始の信号が装置Ａに送ら
れ、装置Ａは新しいデータを伝送装置１と伝送線
路３を介して受信側伝送装置２へ送り、バツフア
メモリ４にデータを蓄わえる。蓄わえられたデー
タは端末装置Ｂによつて逐次使用されるが、デー
タ供給速度が使用速度を若干上廻るようにされて
いるため上限値N1の値になると、端末装置Ｂは
装置Ａに対しデータ転送停止の信号を送る。この
ようにバツフアメモリ４に蓄えられたメモリを端
末装置Ｂは自己の使用ペースに従つた擬似
READをくり返して読み込まれる。
第６図は第５図に示す本発明によるデータ伝送
装置の送信と受信伝送装置内の回路構成をさらに
くわしく示したものである。第６図において、
Ｐ／Ｓは並列・直列変換回路、Ｓ／Ｐは直列・並
列変換回路であり、例えば８ビツトで構成される
データ信号はＰ／Ｓ回路で直列信号に変換され単
一の伝送線路例えば光フアイバで伝送される。尚
送信側制御回路５は送信側装置Ａに擬似RRDY
を発信し、装置Ａのバツフアメモリ４へのデータ
転送を制御し、端末装置Ｂからの使用メモリが
N2を切つたことによるデータ転送停止の信号が
来ればRRDY−ONとしてデータ転送を停止した
り、装置ＡからのREADの信号をデータ回線に
入れて受信側伝送装置Ｂへ送信する。受信側制御
装置回路６は端末装置Ｂに擬似READ信号を発
信し、バツフアメモリに蓄えられたデータを装置
Ｂの要求に応じて供給する。さらに制御回路６は
バツフアメモリの使用中のメモリ数を監視しメモ
リ数が上限値N1を超えた場合はデータ転送停止
の信号を装置Ａに発信し、メモリ数が下限N2を
切つた場合はデータ転送開始の信号を装置Ａに発
信する。尚、第６図に示すものはデータ用伝送線
路３1とステイタス情報用伝送線路３2は分離され
ている。
ところで、バツフアメモリのメモリ数Ｎ、上限
値N1、下限値N2は伝送線路長と信号の伝送速度
によつて決まり、下式の関係にある。
Ｎ≧Na＋２ToL／Te
N1＞N2
Ｎ−N1＞２ToL／Te
N2＞２ToL／Te
ここに、
Na：使用中のバツフアメモリ数、
To：信号が伝送線路の単位長を伝搬する所要時
間例えば、5μsec／Km、
Te：単位メモリ当りのデータ転送時間である。
例えば伝送線路がT0＝5μsec／Kmの光フアイバ
であれば、データ伝送速度が100Mbpsだとこの
光フアイバに１Km当り500bitのデータが乗ること
になり、伝送速度アツプの場合に線路長の遅れ効
果を有効に利用してバツフアメモリを最小限度に
することができる。このようなことは、従来の伝
送速度が例えば9600bpsでは全く考えなくても良
かつた。
尚、N1、N2は（N1−N2）が多い程データ転
送停止頻度は少なくなるが端末装置のメモリ使用
数に応じて適当な値に選ばれる。
本発明によるデータ伝送装置によれば従来
CADシステム等でCPUと図面出力装置の配置間
隔は並列信号接続の場合でもたかだか300ｍしか
離すことができなかつたが、本発明によるデータ
伝送装置を使用することによつて、CPUと端末
装置である図面出力装置の間の距離を数Kmから十
数Kmまで離すことが可能となつた。しかもCAD
の場合図面出力速度が直結の場合と同程度に確保
することができた。このためCPUと図面出力装
置等端末装置の施設内設計配置が今迄の様な距離
の制限を考慮することなく行なえるようになつ
た。[Table] An object of the present invention is to provide a data transmission device that eliminates delays in data transfer caused by connecting a transmitting device and a receiving device with a data transmission line. The configuration of the data transmission device according to the present invention that achieves the above object is composed of a transmitting device and a receiving device for data transmission, and a transmission line having a length of L that connects the transmitting device and the receiving device. A buffer memory is provided in the receiving device, and when the number of memories being used by the receiving device in the buffer memory exceeds a specific number N1 , the receiving device sends a signal to the transmitting device to stop data transfer, and stops using the buffer memory. The device is characterized in that when the internal memory reaches a specific number N2 , the receiving device sends a signal to the transmitting device to start data transfer. However, the buffer memory number N, the specific number N 1 ,
There is the following relationship between N2 . N≧Na+2×ToL/Te N 1 >N 2 N−N 1 >2×ToL/Te N 2 >2ToL/Te Where, Na: Number of buffers in use, To: Propagation time per unit length of transmission line , Te: unit memory transfer time, . With the above configuration, a hysteresis determined by the specific numbers N 1 and N 2 is provided between the transmission of the signal to stop data transfer and the transmission of the signal to start data transfer, and the length L of the transmission line is also kept at the same level as the buffer. This allows the buffer memory to be minimized. One embodiment of a data transmission device according to the present invention will be described with reference to the drawings. FIG. 5 shows a block diagram of one embodiment of a data transmission device according to the present invention. In Figure 5, A is
A device that transmits data such as a CPU, 1 is a transmitting side transmission device connected to device A by a parallel signal line, 2 is a receiving side transmission device connected to a terminal device B such as a drawing output device by a parallel signal line, 3 4 is a transmission line such as an optical fiber having a length L that connects the transmitting/receiving transmission device, and 4 is a buffer memory provided in the receiving side transmission device 2. In FIG. 4, unlike the case shown in FIG. 2, in which the readability of the receiving side device is checked each time the data is transferred, a buffer memory 4 is provided in the receiving side transmission device 2, and the data of the device A is stored at the terminal. Device B sequentially uses the memory transferred from device A stored in buffer memory 4, and when the number of used memories in the buffer memory falls below the lower limit N2 , a signal to start data transfer is sent from terminal device B to device A. The device A sends the new data to the receiving side transmission device 2 via the transmission device 1 and the transmission line 3, and stores the data in the buffer memory 4. The stored data is sequentially used by terminal device B, but since the data supply rate is set to slightly exceed the usage rate, when the upper limit value N1 is reached, terminal device B uses device A sends a signal to stop data transfer. The terminal device B uses the memory stored in the buffer memory 4 in a pseudo manner according to its own usage pace.
It is read by repeating READ. FIG. 6 shows in more detail the circuit configuration within the transmitting and receiving transmitting device of the data transmitting device according to the present invention shown in FIG. In Figure 6,
P/S is a parallel/serial conversion circuit, and S/P is a serial/parallel conversion circuit. For example, a data signal consisting of 8 bits is converted into a serial signal by the P/S circuit and connected to a single transmission line, such as an optical fiber. Transmitted by . In addition, the transmitting side control circuit 5 provides a pseudo RRDY to the transmitting side device A.
and controls the data transfer to the buffer memory 4 of device A, and the memory usage from terminal device B is
When a signal to stop data transfer is received by turning off N2 , the data transfer is stopped by setting RRDY-ON, or the READ signal from device A is put into the data line and transmitted to transmission device B on the receiving side. The receiving side control device circuit 6 transmits a pseudo READ signal to the terminal device B, and supplies the data stored in the buffer memory in response to a request from the device B. Furthermore, the control circuit 6 monitors the number of buffer memories in use, and if the number of memories exceeds the upper limit N1 , it sends a signal to device A to stop data transfer, and if the number of memories falls below the lower limit N2 , Sends a signal to device A to start data transfer. In the case shown in FIG. 6, the data transmission line 3 1 and the status information transmission line 3 2 are separated. By the way, the number of buffer memories N, the upper limit value N 1 , and the lower limit value N 2 are determined by the transmission line length and the signal transmission speed, and have the following relationship. N≧Na+2ToL/Te N 1 >N 2 N-N 1 >2ToL/Te N 2 >2ToL/Te Where, Na: Number of buffer memories in use, To: Time required for the signal to propagate through the unit length of the transmission line, e.g. , 5μsec/Km, Te: Data transfer time per unit memory. For example, if the transmission line is an optical fiber with T 0 = 5 μsec/Km, if the data transmission speed is 100 Mbps, 500 bits of data will be transferred to this optical fiber per 1 km, and when the transmission speed increases, the delay effect of the line length will be affected. Buffer memory can be minimized by making effective use of the buffer memory. If the conventional transmission speed was, for example, 9,600 bps, there was no need to consider such matters. Note that N 1 and N 2 are selected to be appropriate values depending on the number of memories used by the terminal device, although the frequency of data transfer stop decreases as (N 1 −N 2 ) increases. According to the data transmission device according to the present invention, conventional
In CAD systems, etc., the distance between the CPU and the drawing output device could only be 300 m at most even in the case of parallel signal connections, but by using the data transmission device of the present invention, the distance between the CPU and the terminal device can be increased. It has become possible to increase the distance between drawing output devices from several kilometers to more than ten kilometers. Moreover, CAD
In this case, the drawing output speed was able to be maintained at the same level as in the case of direct connection. This has made it possible to design and arrange CPUs and terminal devices such as drawing output devices within the facility without having to consider the distance limitations that existed up until now.
第１図は従来のデータ処理装置の構成図、第２
図は第１図に示す中央と端末を伝送線路で結んだ
場合の回路構成図、第３図は第１図の回路構成の
場合のデータ転送のタイムチヤート、第４図は第
２図の回路構成の場合のデータ転送のタイムチヤ
ート、第５図は本発明のデータ伝送装置の回路構
成図、第６図は第５図のものの伝送装置部分をさ
らにくわしく示した回路構成図である。
図において、１は伝言側伝送装置、２は受信側
伝送装置、３は伝送線路、４はバツフアメモリ、
５と６は制御回路である。
Figure 1 is a configuration diagram of a conventional data processing device;
The figure is a circuit configuration diagram when the center and terminals shown in Figure 1 are connected by a transmission line, Figure 3 is a data transfer time chart for the circuit configuration shown in Figure 1, and Figure 4 is the circuit shown in Figure 2. FIG. 5 is a circuit configuration diagram of the data transmission device of the present invention, and FIG. 6 is a circuit configuration diagram showing the transmission device portion of FIG. 5 in more detail. In the figure, 1 is a message side transmission device, 2 is a receiving side transmission device, 3 is a transmission line, 4 is a buffer memory,
5 and 6 are control circuits.
Claims (1)
装置と、上記送信側装置並びに受信側装置を結ぶ
長さＬなる伝送線路とからなり、上記受信側装置
にバツフアメモリを設け、 バツフアメモリ数Ｎ、特定数N1、N2の間に下
記の関係があり、 Ｎ≧Na＋２×ToL／Te N1＞N2 Ｎ−N1＞２×ToL／Te N2＞２ToL／Te ここに、 Na：使用中のバツフア数、 To：伝送線路の単位長当りの伝搬時間、 Te：単位メモリの転送時間、 該バツフアメモリに受信側装置の使用中のメモ
リが特定数N1を超えたときに上記受信側装置は
上記送信側装置にデータ転送停止の信号を送り、
使用中のメモリが特定数N2を切つたときは上記
受信側装置は上記送信側装置に対してデータ転送
開始の信号を送ることを特徴とするデータ伝送装
置。 ２ 上記送信側装置が送信装置と送信側伝送装置
とからなり、上記受信側装置が受信装置と受信側
伝送装置とからなり、上記バツフアメモリが上記
受信側伝送装置に配置されていることを特徴とす
る特許請求の範囲第１項記載のデータ伝送装置。[Scope of Claims] 1. A transmitting device and a receiving device that perform data transmission, and a transmission line having a length of L that connects the transmitting device and the receiving device, and a buffer memory is provided in the receiving device, There is the following relationship between buffer memory number N, specific numbers N 1 and N 2 , N≧Na+2×ToL／Te N 1 ＞N 2 N−N 1 ＞2×ToL／Te N 2 ＞2ToL／Te Here , Na: Number of buffers in use, To: Propagation time per unit length of transmission line, Te: Transfer time of unit memory, When the buffer memory in use on the receiving side device exceeds a specific number N1 The receiving device sends a data transfer stop signal to the transmitting device,
A data transmission device characterized in that when the number of memories in use falls below a specific number N2 , the receiving device sends a data transfer start signal to the transmitting device. 2. The transmitting device includes a transmitting device and a transmitting device, the receiving device includes a receiving device and a receiving transmitting device, and the buffer memory is disposed in the receiving transmitting device. A data transmission device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57213974A JPS59104845A (en) | 1982-12-08 | 1982-12-08 | Data transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57213974A JPS59104845A (en) | 1982-12-08 | 1982-12-08 | Data transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59104845A JPS59104845A (en) | 1984-06-16 |
| JPH0410775B2 true JPH0410775B2 (en) | 1992-02-26 |
Family
ID=16648143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57213974A Granted JPS59104845A (en) | 1982-12-08 | 1982-12-08 | Data transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104845A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685518B2 (en) * | 1985-06-28 | 1994-10-26 | ソニー株式会社 | Information service system |
| JPS63182935A (en) * | 1987-01-26 | 1988-07-28 | Hitachi Cable Ltd | Hand shake communication system for line exchange loop network |
| US5361841A (en) * | 1993-05-27 | 1994-11-08 | Shell Oil Company | Drilling and cementing with blast furnace slag/polyalcohol fluid |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787254A (en) * | 1980-11-19 | 1982-05-31 | Hitachi Ltd | Data repeating installation |
| JPS57173255A (en) * | 1981-04-17 | 1982-10-25 | Mitsubishi Electric Corp | Facsimile transmitter |
-
1982
- 1982-12-08 JP JP57213974A patent/JPS59104845A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787254A (en) * | 1980-11-19 | 1982-05-31 | Hitachi Ltd | Data repeating installation |
| JPS57173255A (en) * | 1981-04-17 | 1982-10-25 | Mitsubishi Electric Corp | Facsimile transmitter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59104845A (en) | 1984-06-16 |
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