JPH0685518B2 - Information service system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of Invention C Conventional Technology D Problems to be Solved by the Invention E Means for Solving Problems F Action G Example G ₁ Outline of Information Service System G ₂ Information Service System basic system shows a schematic diagram (FIG. 1) G ₃ of the inserted transmission signal to the broadcast signal format (second
Figure) G ₄ shuffling previous service data unit SD format (FIG. 3) G ₅ service data unit SD and service data SDA which follow
(Figure 4) G ₆ baud rate section BR description (Figure 5) G ₇ control data section CD description (Figure 6) G ₈ sync code SC description (Figure 7) G ₉ control Data CDA explanation (Fig. 8) G ₁₀ Addressing explanation (Fig. 9) G ₁₁ Addressing data AD format (Fig. 9) G ₁₂ Reason for using two kinds of key codes G ₁₃ Setting multiple addressing modes Reason for G ₁₄ System diagram of receiver 30 (Fig. 11) G ₁₅ Decoder 50 circuit description (Fig. 12) G ₁₆ Decoding process of service data SDA G ₁₇ Decoding process in addressing mode G ₁₈ Sync code detector 60 And the explanation of the judgment circuit section 59 (13th
(Fig.) G ₁₉ Description of catch-up operation H Effect of the invention A Industrial field of use The present invention relates to a novel information service system that can conceal information data and receive information service for a fee.

B. Summary of the Invention The present invention relates to this information service system, and in particular, a decoder provided on the receiving side is provided with a memory having a transmission capacity larger than the data transmission rate at the normal time, and this memory is full at the time of the normal data transmission. When the data transmission is interrupted due to a data transmission failure, the data stored in the memory is used only until the data transmission failure is recovered, and the data is sent to the data processing system provided in the subsequent stage. It was done.

This makes it possible to avoid the lack of data due to a data transmission failure.

C Conventional Technology As an information service system capable of providing specific information only to a specific subscriber, a system using a dedicated line or the like has been conventionally known.

Specifically, the specific information transmitted from the database station using the dedicated line is received by the decoder provided on the subscriber side so that the information on the station side can be provided. There is.

D. Problems to be Solved by the Invention By the way, in the above information service system, if the number of subscribers is remarkably increased, it becomes difficult to secure a dedicated line, which is a limitation.

In addition, as information provided by the bureau side, when a large amount of money is required for collecting the information and information transmission equipment such as stock information and commodity transaction information in multiple markets, non-subscribers Needs to come up with a system where the information cannot be easily decoded. In the conventional information service system, the information can be easily obtained only by installing the decoder on the subscriber side, so that the information is easily available to non-subscribers.

In such a case, it is necessary to take an advanced eavesdropping prevention means, but conventionally such a concealment means has not been adopted.

Further, conventionally, once a decoder is purchased, information can always be provided as long as the decoder is owned. However, as described above, when the information collection cost and the facility cost for operating the station become enormous, it is preferable to pay the information provision.

Therefore, for a large number of subscribers, the confidentiality of information is ensured, and a paid information service system has not yet been developed.

In consideration of such a point, the present invention has a simple structure of a problem in constructing an information service system capable of realizing confidentiality of information and a paid service of information, that is, lack of data on the decoder side due to occurrence of data transmission failure. It can be avoided in.

E Means for Solving the Problems In order to solve the above problems, the present invention employs the following means.

That is, in the present invention, as described above, the service data and the key code transmitted from the database station are received by the decoder provided on the subscriber side, and the key code transmitted by decoding these data is received by the receiving side. The information service system is designed so that the specific information service sent from the database station can be received only when it matches the key code of.

In this information service system, according to the present invention, at least the decoder side is provided with a memory having a transmission capacity larger than the data transmission rate in the normal time, and the memory is brought into a full state at the time of normal data transfer to prevent a data transmission failure. When the data is interrupted, the data stored in the memory is used to be sent to the data processing system provided in the subsequent stage only while the data transmission failure is recovered.

F function In this configuration, in order to always secure the normal transmission rate, the transmission system is set so that the transmission capacity larger than the transmission rate during the normal operation can be transmitted.

When a data transmission failure occurs, data processing is executed using the data stored in the memory.

When the data transmission failure is recovered, data is sent from the processor side to the decoder side at a transmission rate higher than the normal transmission rate. When the memory on the decoder side becomes full, it automatically returns to the normal transmission rate.

In this way, it is possible to avoid data interruption even if a data transmission failure occurs.

G. Embodiment FIG. 1 is a schematic block diagram showing an example of an information service system which is a premise of the present invention.
An outline of the information service system according to the present invention will be described.

G ₁ Outline of Information Service System This information service system receives the service data and the key code sent from the database station by the decoder provided on the subscriber side as described above, and decodes these data. A system designed to receive a specific information service sent from a database station only when the sent key code matches the key code on the receiving side.

First, the transmission data is shuffled to prevent wiretapping.

This is because, as described above, it is difficult for non-subscribers to obtain information, and only specific subscribers can be provided with specific information.

Second, information services are charged.

In other words, the system is such that only the person who paid the fee can receive the information service.

Therefore, the system defines a receiving contract period, for example, a monthly receiving contract period, and the information can be continuously provided by updating the contract period.

Payment and non-payment of charges for each reception contract period is checked by the station side, and in case of non-payment, the addressing on the decoder side described later is the same as data transmission so that the information service is automatically stopped. It is executed by various means.

Therefore, after addressing, the key code is transmitted at the same time as the above data transmission, and only when the transmitted key code matches the key code stored in the decoder on the receiving side (key code stored by addressing) Can be provided.

System diagram showing basic basic configuration of G ₂ information service system Now, FIG. 1 is a configuration diagram showing an example of a novel information service system 10 which is a premise of the present invention.

10A is a database station, 10B is a ground relay station, and 10C is a receiving station (subscribing station). The transmission signal formed by the database station 10A is a predetermined one of the vertical blanking period of the broadcast signal.
A broadcast signal (the format of which is shown in FIG. 2) inserted in a horizontal line or several horizontal lines and having a transmission signal inserted therein is transmitted to a broadcasting satellite 22, and from the broadcasting satellite 22 to a ground relay station 10B. This broadcast signal is transmitted.

The ground relay station 10B has a BS antenna 24, and an SHF band broadcast signal received by the BS relay 24 is transmitted via a BS converter 25 to a transmitter 26.
UHF or V, which is supplied to the broadcast signal suitable for retransmission
This is converted to the HF band broadcast signal and this is also used by the antenna 27.
Is transmitted to the plurality of receiving stations 10C.

The broadcast signal received by the antenna 29 of the receiving station 10C is received by the receiver 3
At 0, the transmission signal inserted in the broadcast signal is decoded, the service data obtained as a result of the decoding is supplied to the personal computer 31, necessary information is selected, and this is supplied to the monitor 32 and the data is supplied. To be monitored.

Assuming that a maximum of 8 horizontal lines (8 channels) is used as a transmission signal to be inserted in a broadcast signal, it is possible to install a plurality of database stations in the database station 10A, so that eight databases 11A to 11H are installed according to the number of channels described above. it can.

Large-scale host computers 12A to 12H and billing computers 13A to 13H corresponding to the databases are installed in the databases 11A to 11H. The host computer collects stock information, product transaction information, etc. for each region to form service information data (hereinafter referred to as service data) to be provided to the customer.

The billing computer manages the reception contract status of subscribers who have subscribed to each database, and billing data corresponding to the reception contract and its cancellation, that is, addressing data is formed for each reception contract period.

The service data and billing data are supplied to the corresponding processors (front-end processors, FEPs) 14A to 14H by using a telephone line or a dedicated line. One processor can process one channel of data, and one channel of data channel corresponds to one horizontal line inserted in the video signal.

Each of the processors 14A to 14H has eight data input ports, and a maximum of eight service levels can be multiplexed on one channel. Therefore, as shown in FIG. 1, the service data transmitted from the first database 11A can be input to the ports of all the processors 14A to 14H. The same applies to the service data from the second to eighth databases 11B to 11H. Therefore, eight processors 14A to 14H can handle a maximum of 64 types of service data.

A host computer 15 for generating control data, which will be described later, is connected to each of the processors 14A to 14H, and shuffled transmission signals are formed based on these data.

The transmission signal is superimposed on the video signal supplied to the terminal 18 in the data insertion circuit 17. Which horizontal line in the vertical blanking period the transmission signal is inserted into is determined by a control signal (not shown) supplied thereto.

The broadcast signal with the transmission signal inserted is SHF at the transmitter 20.
After being converted into a band signal, the BS antenna 21 transmits it to the broadcasting satellite 22.

G ₃ Format of Transmission Signal Inserted in Broadcast Signal Now, FIG. 2 shows an example of the format of the transmission signal (one horizontal line) to be superimposed on the broadcast signal. SD (21 bytes in this example), check bit part for this service data part SD
CB (10 bytes), control data section CD (1 byte) inserted in front of service data section SD, bit sync (2 bytes) BIS and byte sync BYS (1 inserted in front of control data section CD Byte) and a channel address portion CA (1 byte) inserted between the synchronization data portion and the control data portion CD.

The synchronous data part is clock data inserted to decode the transmission signal.

The channel address portion CA is data indicating the type of used channel.

The control data section CD is data indicating shuffling block data, shuffling map data, etc. for the shuffled service data section SD,
This control data section CD is also transmitted in a shuffled state.

The service data section SD is data used for customer services such as securities information.

G ₄ Format of service data part SD before shuffling Fig. 3 shows the format of service data part SD before shuffling.

In this example, the service data section SD is composed of 62 fields (62 lines) as one data block, and one data block is further divided into _eight service blocks (SB _{1 to} SB ₈ ). Data inserted in one horizontal line in one data block is 31 bytes, and one service block is composed of 31 bits.

The data inserted into the first field before shuffling is the header data part HD, and the data below the second field is the service data SDA.

The header data part HD is used as decoding information (service data multiplexing information, etc.) for the service data SDA inserted in the second field and below.

G ₅ Service data section SD and subsequent service data SDA
4 is a format showing the relationship between the service data section SD and the service data SDA that follows it.

That is, in the first horizontal line corresponding to the first field, the header data section HD having the format shown in the figure is located for each service block. Header data part HD
, Service level section SL (3 bits) This indicates the data on which channel the service data is inserted.

, Baud rate part BR (2 bits) This is because the configuration of the service block at the time of transmission differs depending on the baud rate. The details will be described later.

, SYNC / ASYNC (SYNC / ASYNC) part SAS (1 bit) This data indicates whether the data is transmitted in the synchronous mode or the asynchronous mode.

, Key code part KC (4 bits) This is a key code inserted for each service of the month so that only the subscriber who has paid the fee can receive the information service. The service of the data is executed by comparing with the key code sent to, and by matching.

, Line data end part LDE (6 bits) Since each block has a different block length forming one service block, it is data indicating the number of constituent lines in that block.

In the case shown in FIG. 4, since the service block ends at the 58th line, in this case, data indicating that the 58th line is the last line is inserted as the line data end part LDE. .

, Bit data end part BDE (5 bits) This is data indicating the number of bits in the final line of the service block. In the example shown in FIG. 4, the 10th bit is the final bit, so this final bit is the bit data. Expressed in the end part BDE.

It is set to a format like.

Even after the shuffling, the header data part HD of such a format is applied to the first horizontal line of each service block.

G ₆ Description of baud rate section BR The configuration of the service block during transmission differs depending on the baud rate section BR.

For example, if the maximum transmission capacity is 9600 baud,
When the transmission rate of baud is set, as shown in FIG. 5A, the data composed of the first to eighth service blocks SB _{1 to} SB ₈ is only 1-channel data, and when it is composed of 4800 baud, As shown in FIG. 9B, 2-channel data can be transmitted. Examples of other baud rates are shown in Figures C and D. However, other than this, 2400 baud and 1200
Since the baud can be selected, it can be easily understood that combinations other than the exemplified combinations can be adopted.

The header data part HD, the service data SDA, and the check bit part CB described above are shuffled within each line and also shuffled between 62 lines.

However, even after the shuffling, the processor 14A to 14H execute processing such that the above-mentioned header data portion HD is located in the service data portion SD inserted in the first horizontal line of one block data.

G ₇ Description of control data section CD FIGS. 6 to 8 are used to explain the contents of the control data section CD.

The control data section CD is also shuffled except for a part of the data, and an example of the configuration of the control data section CD corresponding to one block after deshuffling is shown in FIG.

The control data section CD has a variable data structure, which includes: sync code SC (1 byte), control data CDA (fixed length of 48 bytes), dummy code DC (variable length code of 4 to 11 bytes). Configured as.

The sync code SC is used as data information for deshuffling the shuffled control data portion CD and data information indicating a division of the control data portion CD. When 64 kinds of sync codes are used as the sync code SC, the control data section CD can select 64 kinds of shuffling patterns.

G ₈ Sync code SC description The sync code SC is not shuffled. The sync code SC is regarded as the sync code SC only after inserting the same code three times in succession. That is, as shown in FIG. 7, the sync code SC is inserted from the first line to the third line.

The 48-byte data following the sync code SC becomes the control data CDA.

The control data CDA is the decoder 50 (see FIG. 12).
The shuffling block information of the service data part SD and the shuffling map information of the service data part SD are transmitted.

G ₉ Description of control data CDA Fig. 8 shows an example of the control data CDA format (before shuffling).

The control data CDA consists of 4 bytes as the basic unit, and the previous 2 bytes are the shuffling block data SB.
The last 2 bytes are the shuffling map data SM.

First, the shuffling block data SB is formed by a total of 6 bits of 2 bits of the first byte and 4 bits of the second byte. The check code CC inserted in each byte is
Shuffling block data inserted in each byte
For SB data check.

The shuffling map data SM is formed by a total of 6 bits of 2 bits of the 3rd byte and 4 bits of the 4th byte. The check code CC inserted in each byte is for checking the shuffling map data SM inserted in each byte.

The same code as this control data CDA is used 5 times (total 2
0 bytes), and therefore the format before shuffling is as shown in FIG.

In this way, the same data is used five times in order to avoid a malfunction due to noise mixed in during transmission. In this example, the control data CDA of five times is majority-determined to give the larger data. It is used as control data CDA.

The control data section CD has a fixed length of 48 bytes, and the data following the control data CDA is used as optional data. Therefore, the data slot of 20 bytes or more is not used as control data.

The dummy code DC inserted in the rear part of the control data CDA has a variable length, so that the code length of the entire control data part CD has a variable length configuration. In this example,
The control data section CD is variable over 55 to 62 fields, so that the dummy code DC has any code length between 4 to 11 fields. As a result, the control data section CD has one block consisting of 55 to 62 fields.

For the dummy code DC, a code pattern not used in the sync code SC is used. This is because the sync code SC is accurately separated from the control data section CD.

When the control data section CD is configured to have a variable length, it becomes difficult to detect the control data section CD inserted in one block, which complicates the data deshuffling process by the non-subscriber and keeps the information confidential. Will be strengthened.

In addition, although the sync code SC that has not been shuffled is included in the control data section CD, the sync code SC
Even if the SC is not shuffled, the control data section CD itself cannot be decoded easily because the code length of the control data section CD itself is variable.

However, the decoder installed in the subscriber is
Since there is a map of the deshuffling pattern that detects the SC and deshuffles the control data section CD, the control data section CD
The deshuffling process of can be performed accurately.

In this case, the data length (48 bytes) following the sync code SC
Is constant, it is relatively easy for the decoder side to detect this sync code SC.

As mentioned above, the control data section CD is a sync code
By shuffling according to the type of SC, and decoding the shuffling map data SM included in the shuffled control data CDA, the service data section SD is deshuffled.

The shuffled service data portion SD and control data portion CD are inserted into one horizontal line in units of 31 bytes to form the transmission signal format shown in FIG. In this case, the synchronization data (see FIG. 2) inserted into each horizontal line is not shuffled.

G ₁₀ Addressing Description Before sending the transmission signal shown in FIG. 2, addressing is performed on the decoder 50 provided in the receiver 30 as a pre-stage.

Addressing is also performed using broadcast signals as well as transmission signals. In this case, of the transmission signals shown in FIG. 2, addressing data A instead of service data SDA is used.
The one with DA inserted is used as the transmission signal.

First, an outline of addressing will be described.

The plurality of decoders provided in the plurality of receiving stations 10C are provided with non-volatile memories for storing key codes, and the key codes transmitted at the time of addressing are stored in these memories. Decoders are given consecutive addresses, and when an address that identifies the decoder (in some cases, an address map is used) is transmitted, the key code waits and the binary code of the address map is "1". , "0" automatically controls the key code writing status.

For example, if the binary code is "1" and the write enable is enabled, when the binary code of the address map is "1", the key code is written in the corresponding decoder. Therefore, in this case, when the binary code is "1", the subscription fee has been paid.

When the binary code is “0”, the reception contract fee has not been paid, and in that case, the key code is not stored in the corresponding decoder.

The addressing is performed for each reception contract period, and the execution period is performed by using a predetermined period before the reception contract period (there may be a bite into the reception contract period of the next month).

As shown in Fig. 2, the key code for the current month is included in the transmitted signal.
Since the KC is inserted, the information service can be received only when the key code KC and the key code stored in the decoder match.

Therefore, the addressing data AD has a format as shown in FIG.

G ₁₁ Addressing Data AD Format The addressing data AD is also composed of 62 fields as one block, and shuffling processing is performed for concealing information. The format shown in FIG. 9 is for one horizontal line before shuffling.

The addressing data AD has the following structure.

, Key code KC (1 byte) Two types of key codes are sent. The key code consists of 4 bits, one is the key code for the current month, and the other is the key code for the next month.

If the decoder receives the service data SDA, this 2
If one of the two key codes is stored in memory,
The service status is entered.

, Address data AD ₁ and AD ₂ (3 bytes each) Address data for specifying the decoder. The data from address data AD ₁ to AD _{2 is} 100
You can specify the decoder address in units of units.

However, the address of each decoder cannot be specified with this address data.

, Address map data AM (13 bytes) Based on the address of address data AD ₁ (AD ₂ ) 104
An address is specified for each decoder.

The first 1 bit of the address map is the address data AD ₁
The addresses of the respective decoders are successively and consecutively designated such that the address is for the same decoder as (AD ₂ ), and the next 1 bit is the address for the next decoder.

Address data AD ₁ , AD ₂ and address map data AM
Will have different addressing specifications depending on the mode code MD described below.

, Mode code MD (2 bits) This is a code for specifying the mode during addressing.

Since it has a 2-bit configuration, the following four types of addressing modes can be selected.

(A), mode 0 This is a collective addressing mode in which data service is not performed to all the decoders having the addresses specified by the address data AD ₁ and AD ₂ .

In this case, the bits of the address map data AM are all set to "0", and the transmitted key code KC is not stored in the memory of the decoder.

(B), Mode 1 A mode in which a data service is provided to the decoder specified by the address of the address data AD ₁ and the decoder specified by the address of the address data AD ₂ (hence, only two decoders are specified). Is.

(C) The mode 2 address data AD ₁ , AD ₂ are set to the address data AD ₁ , A ₂ for each of 104 decoders whose base points are addresses.
"1" in the address map AM followed by D _2, to run the addressing by "0".

In this case, the address data AD ₁ and AD ₂ are the same address data.

When the address data AD ₁ specifies a decoder in the 100s, the first bit of the address map AM specifies the decoders in the 100s, and the subsequent bits specify the 101st decoder.

When the bit is "1", the key code (two types) described above is stored in the memory of the corresponding decoder.
Is memorized.

On the other hand, when the bit is "0", the key code is not stored.

(D), mode 3 The opposite of mode 0, the addressing is collectively performed on all the decoders designated by the address data AD ₁ and AD ₂ .

Therefore, the key code is stored in those decoders. In this case, the address map data AM is
All are set to "1".

, Service level code SL (6 bits) This is a code indicating which host computer data has been inserted and transmitted. The upper 3 bits are assigned to the data channel, and the lower 3 bits are assigned to the service level.

In the above example, since transmission is performed using eight host computers and eight horizontal lines (8 channels), a total of 64 service levels can be specified.

G ₁₂ Reasons for using two kinds of key codes In the above addressing format, two kinds of key codes KC are transmitted at the same time for the following reasons.

Addressing is executed in units of the reception contract period before the contract period expires. For example, if the contract period is defined on a monthly basis, the addressing for the next month will be executed in the current month. The key code (the one in the transmission signal) sent during the contract period has a different pattern from the previous key code, so if you send only the key code (one type) for the next month during addressing,
The following inconvenient situations occur.

For example, as shown in Figure 10, the current month is January, and 1
It is assumed that KC ₁ is used as the month key code KC and KC ₂ is used as the _February key code KC.

In this case, addressing with the key code KC ₂ is executed in the _second half period T of January. If the particular decoder has paid the subscription fee in January and February, the particular decoder stores the key code KC ₂ in a predetermined memory when addressing in the mode 2. .

By this memory operation, KC ₂ is stored in this memory in place of the January key code KC ₁ .

Therefore, the key code will be changed to KC ₂ from the latter half of January, so you will not be able to receive the data service in the latter half of the period after addressing even though the subscription fee has been paid. Inconvenience occurs.

On the other hand, when addressing is executed at the same time by sending out the key codes KC ₁ and KC ₂ of the current month and the next month simultaneously during addressing as described above, the key code K
Since C ₁ and KC ₂ are both stored in memory, the data service for the month can be received even after addressing, and the above inconvenience is solved.

G ₁₃ Reasons for setting multiple addressing modes The reason why multiple addressing modes can be selected is as follows.

For example, when the receiving station 10A having all the decoders of addresses 0 to 1000 is unpaid for the contract fee, the batch addressing by the mode 0 is performed more than the case where the addressing is individually performed by the mode 2. This can greatly reduce the time required for addressing.

For the same reason, when the receiving contract fee of a certain receiving station 10A is paid, if the addressing in the mode 3 is executed, the addressing is collectively performed in this case as well, so that the addressing time can be greatly shortened. Is.

However, when the payment of the reception contract fee varies depending on the address, by selecting the mode 2, it is possible to perform the addressing according to the contract state of each reception station 10A.

In addition, when addressing is performed for a specific receiving station among a plurality of receiving stations 10A, it is necessary to perform it by mode 2, but if the mode 1 can be selected as described above, it is possible to specify Since only the receiving station of is addressed immediately, the addressing time can be shortened as compared with the case of selecting the mode 2.

Therefore, even if there are many subscribers, the addressing time for all the subscribers can be shortened by selecting the addressing mode according to the reception contract status.

FIG. 11 shows an example of a receiver 30 provided in the receiving station 10A for receiving a transmission signal having the above format and receiving a specific data service.

G ₁₄ Receiver 30 system diagram The broadcast signal received by the antenna 29 is supplied to the all-channel tuner 40 and converted into a television signal in a predetermined frequency band, which is a ghost canceller 41.
And is subjected to ghost cancellation processing to avoid malfunction of data extraction.

The output is supplied to the data separation circuit 42, and the transmission signal inserted in the broadcast signal is extracted and separated. The extracted transmission signal is supplied to the decoder 50 and the decoding process of the service data SDA and the like is executed. The service data SDA is made into a code form conforming to the standard of the personal computer 31, and then supplied to the personal computer 31 via the interface 43.

Reference numeral 44 is a control system, which is composed of a controller 45 and a keyboard 46 for giving commands to the controller 45. 47 is a power supply device.

Circuit Description of G ₁₅ Decoder 50 FIG. 12 is a system diagram showing an example of the above-described decoder 50. The transmission signal separated by the data separation unit 42 is extracted by the byte sync unit 51 from the byte sync BYS. .

To detect the byte sync BYS, a gate signal is generated in advance by the gate pulse generator 52 based on the horizontal and vertical synchronization signals HD and VD and the clock signal CK, and the gate signal is gated in the vicinity of the byte sync BYS and then detected.

When the byte sync BYS is detected, the detection signal is input to the gate pulse generator 52, and the gate for extracting the channel address CA, the control data part CD, the service data part SD, the addressing data AD, etc. with the byte sync BYS as a reference. A signal is created.

The channel address data CA extracted by the channel address gate unit 54 is sent to the error correction (humming) unit 55 and is error-corrected.

Error-corrected 4-bit channel address data
CA is the controller 45 in the channel address comparison unit 56
Is compared with the 4-bit data of the channel address setting sent from, and if they match, a match signal is sent to the gate pulse generator 52.

The gate pulse generator 52 uses this coincidence signal as a reference,
Gate on the insertion timing of the channel address data of the same line in the next field. Similarly, a gate pulse is output to the data gate 57 and the control data gate 58.

The control data section CD extracted by the control data gate 58 has a sync code detecting section 60 for detecting the sync code SC included in the control data section CD.
And 64 kinds of sync codes SC are extracted.

Here, if the same sync code SC is detected over three fields, it is determined as the sync code SC and the determination circuit unit
It is sent to 59 as a sync detection signal. The judgment circuit section 59 is
When receiving this detection signal, a holding signal for holding the sync code SC is sent to the sync pattern holding unit 70.

Further, the gate signal for detecting the sync code of the next control data section CD is sent to the sync code detecting section 60. As a result, the sync code SC is easily detected. The details will be described later.

When the sync code SC is detected, the determination circuit unit 59 performs the deshuffling depending on the type of the sync code SC at the same time when writing the control data CDA itself following the sync code SC to the timing generation unit 72 in the RAM 73. Send a sync detection signal to start.

The deshuffling pattern generation unit 75 receives the pattern code (6 bits) from the sync pattern holding unit 70, and RA
Generates a deshuffling pattern that becomes the write address of M73. The start signal is output from the timing generator 72.

When the control data CDA is read from the RAM 73, it is deshuffled.

For this reading, the reading counter 74 operates in response to a counter start signal from the timing generation section 72, and at the same time, the address switching section 76 is switched to the reading side and the read signal is supplied to the RAM 73.

The read control data CDA is error-corrected by the error correction (hamming) unit 80, and the data block information SB is de-shuffled by the data block information extraction unit 81 by the holding signal generated by the timing generation unit 72. The extraction unit 82 extracts the disshuffling map information SM and uses it as a key signal for reproducing the data portion.

The service data SDA (or the addressing data ADA) that has passed through the data gate 57 is stored in the data buffer 85 and sent to the deshuffling circuit 86, which is controlled by the buffer control unit 87.

The buffer control unit 87 receives the reference signal indicating the position (field) of the sync code in the control data CDA from the determination circuit unit 59, the data block shift information from the data block information extraction unit 81, and receives the service data SD.
A (or addressing data ADA) is stored in the data buffer 85 in units of one block, and then control is performed to send it out.

The deshuffling circuit 86 is a deshuffling information extraction unit.
The deshuffling pattern information SM is input from 82, and the service data is deshuffled. After that, the service data SDA (or the addressing data ADA) is error-corrected by the error correction circuit 91.

G ₁₆ Service data SDA decoding process When the addressing mode detection unit 100 detects a service mode, the error-corrected service data unit
Header data part of the first line of SD (1 data block)
Service level code detector 10 to read HD information
1, baud rate detector 102, sync / async detector 10
3. The data end detection unit 104 and the key code detection unit 105 operate to detect each information.

The detected service level code SL is compared with the service level code sent from the controller 45 in the service level comparison unit 107, and if they match, a match signal is sent to the buffer control unit 108 and the key code comparison unit 109.

The detected key code is compared with a predetermined key code stored at the time of addressing by the key code comparison unit 109, and if they match, a match signal is sent to the buffer control unit 108.

The buffer control unit 108 buffers the necessary data in the RAM 110 according to the service level match signal, the key code match signal, the baud rate information, and the data end information,
The output to the interface 43 is controlled at a constant rate.

The baud rate signal and sync / async signal are also sent to the interface 43.

G ₁₇ Decoding process in addressing mode In addressing mode, each line of the data block is addressing information.

Therefore, for each line, the mode signal MC, the service level code SL, the key code KC, the address data AD ₁ , AD ₂ ,
Detect the address data map AM.

Therefore, in addition to the mode code detection unit 112, a service level code detection unit 121, a key code KC detection unit 122, address data AD ₁ detection unit 123, address data AD ₂ detection unit 124, and an address data map AM A detection unit 125 is provided for each.

Mode code MC detected by the mode code detection unit 112
Is sent to the address data ID comparison unit 113. The address data ID comparison unit 113 compares the sent address data with the ID (address data) unique to each decoder stored in the nonvolatile memory 114. The mode code is a code for processing the address data AD ₁ , AD ₂ , and the address data map AM according to the format before this comparison.

When a match with the output of the decoder ID holding unit 115 is detected, an ID match signal is sent to the memory control unit 116, and the memory control unit 116 stores the key code (two types) at this time in the non-volatile memory 114. . At this time, the address of the nonvolatile memory 114 is the 6-bit information of the service level code (channel address 3 bits, service level 3 bits).
Is.

The address selector 120 selects the service level code SL sent in the addressing mode, and selects the channel address data CA and the service level set value sent from the controller 45 in the service mode.

In the service mode, the key code stored in the set channel address and service level is read from the non-volatile memory 114 and sent to the key code comparison unit 109.

G ₁₈ Description of sync detection unit 60 and judgment circuit unit 59 FIG. 13 is a system diagram showing the relationship between the sync code detection unit 60 and judgment circuit unit 59. The sync code detection unit 60 includes a sync comparison unit 61 and a sync pattern. Each data of the control data section CD, which is composed of a comparison section 62 and is gated by the control data gate section 58, is converted into parallel data of 8 bits by the shift register 65, and then supplied to the sync comparison section 61 to be synced. The pattern of the code SC is compared with which of 64 sync patterns.

If any of the 64 types of patterns match, the match signal from this sync comparison unit 61 is the sync pattern comparison unit.
Supplied to 62. The sync code SC itself is also supplied to the sync pattern comparison unit 62, and it is compared whether or not the same sync pattern and the coincidence signal have been continuously input three times.

When the same sync pattern is supplied over three fields, the sync pattern comparison unit 62 outputs a sync detection signal.

The sync detection signal is supplied to the determination circuit unit 59. The judgment circuit section 59 is composed of a counter timer, to which a vertical synchronizing pulse VD is supplied as its clock. The sync detection signal is used as a start signal for the counter timer, and the count operation is started by the sync detection signal.

When the counter timer counts 48 vertical synchronizing pulses VD, a "H" gate signal is output. As a result, the final field of the control data CDA of 48 bytes following the sync code SC is detected.

Therefore, 48 of the control data section CDs
“L” between fixed byte control data CDA
Then, the gate signal which becomes "H" is formed in this judgment circuit section 59 between the variable length dummy code DC and the 3-byte sync code SC following it.

The gate signal is supplied to the sync pattern comparison unit 62 as a masking signal, the pattern comparison operation is prohibited while the gate signal is "L", and the pattern comparison operation is executed only during the "H" period.

Since the sync code SC and the coincidence signal are supplied to the sync pattern comparison unit 62 at any timing of the period when the gate signal is “H”, even if the dummy code DC has a variable length, this dummy code DC The sync code SC following is detected.

When the sync code detection unit 60 and the determination circuit unit 59 are configured in this way, the sync code SC inserted in the control data unit CD is reliably detected even if the control data unit CD has a variable length configuration. be able to.

The control data CDA may include the same pattern as the sync code SC, but the dummy code DC input during the period for performing the pattern comparison operation does not include the same pattern as the sync code SC. The detection accuracy of the sync code SC can be improved in combination with the configuration of.

The holding signal supplied to the sync pattern holding unit 70,
The sync detection signal supplied to the timing generation section 72 and the reference signal supplied to the buffer control section 87 are both output at the same timing as the sync detection signal.

G ₁₉ Description of catch-up operation By the way, when data is interrupted due to a data transmission failure, the catch-up mode described below prevents the lack of data.

For this reason, in the decoder 50 shown in FIG. 12, the capacity of the RAM 110 for data store having a transmission capacity larger than the data transmission rate at the normal time is used.

Now, when the transmission signal received by the decoder 50 is missing for a certain time or longer, the gate pulse generator 52 of the decoder 50 causes various gate signals (byte sync BYS,
It is not possible to obtain the gate signal of the service data section CD.

This is because the horizontal and vertical synchronization signals HD, VD, etc. sent from the data separation circuit 42 are interrupted.

Such data loss may occur even in the middle of a certain data block. At this time, the gate pulse generator
At 52, a data reset signal is sent to the buffer control unit 87 in order to invalidate all the data of the data block which is interrupted on the way. This clears all the data stored in the data buffer 85 up to the middle and waits for the return of the broadcast signal.

In the data processing system in the latter stage of the data buffer unit 85, since there is no data during that time, the data processing unit is in a standby state for data processing.

The same applies to the control data-related processing system, and the data reset signal described above is supplied to the corresponding processing system (disshuffling pattern generation unit 75, data block information extraction unit 81, and deshuffling information extraction unit 82). Is.

Since the RAM 110 for data store can store data for several seconds (for example, about 2 seconds) as described above, even if such data interruption occurs, the stored data can be interfaced for several seconds. It can be sent continuously to 43.

When the transmission failure returns and the transmission state of the broadcast signal returns to normal, the processors 14A to 14H provided on the sending side
Starts transmitting the service data SDA stored in the buffer memory (not shown) provided in the processors 14A to 14H during the lack of data.

The first several fields at the beginning of transmission are idling operations in order to raise the respective gates (54, 57, 58, etc.) of the decoder 50 to normal operation, and substantial data transmission such as service data SDA is prohibited.

When the idling state ends, service data SDA,
Transmission signals such as control data CDA are transmitted.

The service block used for the transmission of service data has a transmission capacity of 9900 baud per second.

During normal operation, service data is sent at 9600 baud per second, but if the above transmission failure occurs, the service data stored in the buffer memory of the processors 14A to 14H will be immediately after the transmission is restored. Until the service data section CD reaches the maximum transmission rate (99
00 baud) is raised and sent to the receiving station.

As a result, the data (service data SDA, etc.) transmitted at the maximum transmission rate is stored in the RAM 110 on the decoder 50 side.

When the service data SDA stored in the buffer memory of the processors 14A to 14H becomes empty, the RAM 110 becomes full. This allows the receiving stations from the processors 14A to 14H to
The transmission rate of the data sent to 11C returns to the normal transmission rate (9600 baud) and returns to the normal transmission mode.

H Effect of the Invention As described above, according to the present invention, in the above-described novel information service system, when a transmission failure occurs, the data stored in the RAM 110 is transmitted, and when the transmission failure is recovered, the data in the RAM 110 is returned. Until the full state is reached, data is transmitted at a transmission rate higher than the normal transmission rate.

According to this, even if a transmission failure occurs, the data is continuously sent to the interface 43 without interruption, so that the personal computer 31 does not have a problem in data processing.

Therefore, the present invention is extremely suitable when applied to the data transmission system of the information service system as described above.

[Brief description of drawings]

FIG. 1 is a system diagram showing a schematic configuration of an information service system according to the present invention, FIG. 2 is a diagram showing a format of a transmission signal, FIG. 3 is a diagram showing a format of a service data section, and FIG. 4 is a service data. Section and the header data section HD, FIG. 5 shows the relationship between the baud rate and the service block, FIG. 6 shows an example of the format of the control data section, and FIG. 7 shows the sync code SC. And the control data CDA, FIG. 8 is a diagram showing an example of the format of the control data CDA,
FIG. 9 is a diagram showing an example of the format of addressing data, FIG. 10 is an explanatory diagram for the sync code SC, and FIG.
FIG. 12 is a system diagram of an essential part showing an example of a receiver, FIG. 12 is a system diagram showing an example of a decoder, and FIG. 13 is a system diagram showing a concrete example of a sync code detecting part and a judging circuit part. 10 is an information service system, 10A is a database station, 10B
Is a ground relay station, 10C is a receiving station, 12A to 12H, 15 is a host computer, 13A to 13H are billing computers, 50 is a decoder, 59 is a judgment circuit section, 60 is a sync code detection section, 87
Is a buffer control unit.

Claims (1)

[Claims] 1. A database station for transmitting service data and a key code, compares a key code stored in a memory with a key code from the database station, and receives the service data only when they match each other. An information service system having a decoder for supplying the data processing unit with data, a first buffer memory provided in the database station for storing the service data and the key code, and the service data and the key provided in the decoder. A second buffer memory for storing a code, wherein the first buffer memory and the second buffer memory operate at a normal data transmission rate and a high-speed data transmission rate higher than the normal data transmission rate, respectively. The above data is configured during normal data transmission. The service data and the key code are transmitted from the first buffer memory of the base station to the second buffer memory of the decoder at the normal data transmission rate,
When a transmission failure occurs between the database station and the decoder, the second buffer memory stores the second buffer memory.
Continues to supply the service data and the key code remaining in the buffer memory of the above to the data processing unit,
When the transmission is restored, the first buffer memory transmits the service data and the key code stored during the occurrence of the transmission failure to the second buffer memory at the high data transfer rate. An information service system characterized by being adapted to perform.