KR101276837B1 - Apparatus for communicating between processor systems operating with different operating frequencies - Google Patents

Abstract

The present invention relates to a method capable of directly communicating between systems operating at different operating frequencies. In other words, the system converts the signal to be transmitted according to the function module and master and slave signal protocols that convert the different operating frequencies to one of the operating frequencies between systems using buses operating at different operating frequencies as the main buses. The state includes a function module and a connection control module for preventing a malfunction that may occur during simultaneous connection. The present invention has the effect of enabling direct communication between systems.

AHB bus, bridge module, operating frequency, semaphore

Description

A device for supporting communication between processor systems operating at different operating frequencies {APPARATUS FOR COMMUNICATING BETWEEN PROCESSOR SYSTEMS OPERATING WITH DIFFERENT OPERATING FREQUENCIES}

1 is a block diagram according to an embodiment of the present invention.

2 is a view for explaining an example of an operating frequency conversion method.

3 is a process flow diagram in accordance with an embodiment of the present invention.

4 is a view for explaining a malfunction that may occur when the simultaneous connection.

5 is a diagram for explaining another embodiment of the present invention.

6 is a block diagram according to still another embodiment of the present invention.

7 shows a state transition diagram showing mutually exclusive connections to the registers of semaphore functions according to one embodiment of the invention.

8 is a view for explaining an example of a method for preventing simultaneous connection to a register of a semaphore function.

The present invention relates to a communication system, and more particularly, to a communication system and a communication method capable of direct communication between processor systems using a bus operating at different operating frequencies.

The communication system comprises at least two processors, depending on the function being performed. A system including a device that operates by receiving a signal from the processor is called a processor system. The processor system uses a bus (BUS) as a passage for signal transmission between the processor and another device.

Each bus connected to each processor operates according to its operating frequency. Direct communication between processor systems using buses operating at different operating frequencies is not possible. Thus, conventionally, shared memory is used for communication between at least two processor systems. The shared memory may be connected to all processors wishing to communicate.

Not only the shared memory but also a control register block for controlling when a processor wishing to connect to shared memory for communication between processor systems using buses operating at different operating frequencies, and notifying the other processor of the shared memory connection status. Interrupt generation register block, register block for setting the time required for each processor to read data in shared memory in operating frequency units, information about transmission of data to be transmitted to the other processor, location of data in memory, and data It consists of a mailbox for telling the size and the like.

According to the conventional communication method, when one processor writes certain data and information about the data to a mailbox in a memory block, and then informs the counterpart processor through an interrupt generation register, the counterpart processor reads the data in the mailbox. After reading the information about, read the data in the memory block.

That is, the conventional communication method uses an interrupt as a handshake between two processors. The use of interrupts is inefficient in terms of software operation because the process of generating and checking interrupts in the software code must be added. In addition, if both processors simultaneously access the counterpart processor, there is a possibility of data collision in shared memory. At this time, according to the prior art, it is not possible to process this automatically (hardware), and use a method of restricting software operation to avoid such a situation. This method puts some burden on the software. Furthermore, memory blocks and register blocks for various controls are added to increase the number of logic gates, thereby increasing the manufacturing cost of a system on chip (SOC).

The present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to provide a method and system capable of direct communication between processors. Another object of the present invention is to provide a more efficient communication system through a method and a system capable of direct communication between the processors. It is still another object of the present invention to provide a communication system that reduces the manufacturing cost of a system on chip (SOC).

The present invention relates to a method that can directly communicate between systems using buses operating at different operating frequencies as the main bus. In particular, the present invention relates to a communication method that can be applied when a subject and an object of communication can establish only a one-to-one relationship according to a bus used in each system. The bus is a passage or transmission path for information that is transmitted and received between a processor constituting the system, a video card, various input / output devices, and peripheral devices. The number of bits that can be simultaneously transmitted through the bus is called a bus width, and the size of data that can be transferred at one time, such as 16 bits or 32 bits, is determined according to the bus width. The bus specification, that is, the bus width and the operating frequency of the bus, determines the bus's data transfer capability (data transfer rate per second), and the overall processing speed of the computer depends on which type of bus is adopted. Personal computer (PC) buses include a 16-bit wide ISA bus, a 32-bit wide EISA bus, and an MCA bus. Apart from these buses, a 32-bit or 64-bit-wide bus that transfers large amounts of data directly between a high-speed CPU running at higher frequencies than the i486 and a high-speed device is called a local bus. Popular local buses include the VL-bus, PCI bus, and AGP, which extends the PCI bus.

In one aspect of the present invention, a method of communication between processor systems using buses operating at different operating frequencies includes: receiving a signal from a first processor system and converting an operating frequency of the received signal to a second processor system; And converting the received signal into a signal form usable by the second processor system, and transmitting the converted signal to the second processor system.

In another aspect of the present invention, a bridge module of a communication system for communication between processor systems using buses operating at different operating frequencies may include converting the operating frequency of the first bus to the operating frequency of the second bus. And a signal conversion module for converting a signal for transmitting the signal received at the first processor system to the second process system.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced.

In the embodiments described below, those applied when the bus used for each processor system is an ARM High Perfomance Bus (AHB) bus used in the high speed bus structure will be described. However, it is obvious that the technical idea of the present invention can be applied to various cases as well as the case of using the AHB bus.

According to the AHB signal transmission protocol, a subject and an object that transmits and receives data through one AHB bus can be classified into a master device and a slave device according to their functions. The master device is typically a processor. The slave device may be a video card connected to the master device, various input / output devices, peripheral devices (for example, a memory controller), and one master device is connected to a plurality of slave devices through the bus. For example, up to 16 slave devices can be connected to one master device.

1 is a block diagram according to an embodiment of the present invention. The communication system 1 shown in FIG. 1 includes a first processor system 10 including a first processor 11 and a second processor system 15 including a second processor 16 and the first processor system ( 10) and a bridge module 14 for performing signal conversion and the like for communication between the second processor system 15. The first processor and the second processor system blocks 10 and 15 use the AHB bus as the main bus of the system and operate at different operating frequencies, and are asynchronous systems. The platform for the System On Chip (SOC) platform ) Is part of the component. Also, the processors may be an ARM9 processor, a DSP processor, or the like.

The first processor system 10 is connected to the first processor 11 and the first processor, the first AHB bus 12 used as a transmission / reception path for data, etc., and the first AHB bus connected to the first AHB bus. And a first slave device 13 capable of transmitting and receiving data with the processor. The second processor system 15 also comprises the second processor 16, the second AHB bus 17 and the second slave device 18. The bridge module 14 performs signal conversion for communication between the first processor system and the second processor system, and is connected to the first AHB bus and the second AHB bus.

First, a case in which the first processor intends to transmit data to a second slave device included in a second processor system will be described. The first processor transmits a connection request signal indicating that data transmission is desired to the first AHB bus, and when the completion signal is received from the first AHB bus, the data transmission is terminated. As described above, a process of transmitting a connection request signal to the AHB bus and receiving a corresponding completion signal is called a communication process. The first processor may perform a communication process by using a first AHB bus, the bridge module 14, a second AHB bus, and the like.

Hereinafter, the bridge module 14 will be described in more detail. Since the first AHB bus and the second AHB bus operate at different operating frequencies, if the signal is transmitted without any processing, a serious error may occur because some or all of the transmitted data may not be received. . Therefore, a signal processing procedure for converting the operating frequency of the transmitting device to the receiving operating frequency is required. A module for converting an operating frequency, that is, a synchronization module (not shown) is included in the bridge module 14.

2 is a view for explaining an example of an operating frequency conversion method. A method of converting an operating frequency signal of the first AHB bus to an operating frequency of the second AHB bus when the first operating frequency of the first AHB bus is faster than the second operating frequency of the second AHB bus will be described with reference to FIG. 2. do. The synchronization module (not shown) receives a data signal from the first AHB bus (20). The first clock signal senses that the data signal has been received and becomes " 1 " for one clock period for the first operating frequency at which the data was received in the state of " 0 " ", (21). Another second clock signal indicates that the first clock signal is converted to " 1 " at the time when one clock cycle ends and becomes "0" again in the state of "0" (22). The third clock signal for the second operating frequency senses that the second clock signal is in the state of "1" in the state of "0" and indicates that the second clock signal is converted to "1" (23). Another fourth clock signal indicates that the third clock signal is switched from " 0 " to " 1 " at the next clock at which the third clock signal is switched to " 1 " (24). Finally, the fifth clock signal represents a signal obtained by subtracting the fourth clock signal from the third clock signal (25). The fifth clock signal refers to a second operating frequency obtained by converting one clock signal shown in. As a result, the result of the conversion from the first operating frequency to the second operating frequency is shown. As described above, the operating frequency can be converted.

According to the signal transmission protocol of the AHB bus, it must be a slave device to receive a signal transmitted from the master device. However, in order to transmit a signal to a slave device connected to a bus having a different operating frequency as described above, a signal conversion process must be performed through the bridge module. Accordingly, the bridge module is provided with a master and slave interface for transmitting a signal transmitted from the master device of the first processor system as well as the synchronization module to the slave device of the second processor system. That is, a slave interface for receiving a signal transmitted from a first processor (master device) and a master interface for transmitting the signal to a second slave device are provided. In addition, a signal conversion module is included to convert the slave interface signal into a master interface signal.

3 is a process flow diagram in accordance with an embodiment of the present invention. According to FIG. 3, when a first processor connects to a slave device in a second processor system, first the first processor sends a bridge device connection request signal in a second processor system to the bridge module and then connects to the slave device. Wait for the completion signal for the request signal (S30). In this case, since the first processor becomes a master device, the first processor transmits a signal to the slave interface of the bridge module according to the AHB transmission protocol. The synchronization module receives the signal from the slave interface and synchronizes with the synchronization circuit according to the operating frequency of the second processor system (S31). The signal conversion module converts the signal to deliver the signal synchronized in the synchronization module to the slave device of the second processor system. At this time, since the master interface receiving the converted signal is a master device with respect to the slave device of the second processor, the master interface also transmits the signal according to the AHB transmission protocol (S32). The signal conversion module may be implemented on the master interface. In this case, a function module for performing the signal conversion may not be provided. Once the connection to the slave device in the second processor is completed, the completion signal is transmitted to the synchronization module through the master interface, the operating frequency is changed in the synchronization module, and then transmitted to the first processor through the slave interface (S33).

The same is true when the second processor connects to a slave device in the first processor system. The second processor may be connected in the first processor system through a slave interface, a synchronization module, and a master interface to the second processor. If the signal conversion module is not implemented on the master interface, it may be provided separately. That is, the connection operation occurs in a direction opposite to the first processor travel direction.

 According to a communication protocol, a connection command signal, data, etc. may be transmitted only after one connection or communication process is completed. In this case, not only is it applied to transmitting the next signal from one processor, but also when the first processor is connected, when the second processor attempts to connect to the slave device in the first processor system, the same communication as that of the first processor is performed as above. Only after the process is completed can the communication be attempted and performed by the second processor. In this case, if two processors are simultaneously connected to a slave device in the other processor system, each of the two processor systems may malfunction due to a protocol in which only one master device and one slave device can be connected at a time in the system. deadlock) may occur.

4 is a view for explaining a malfunction that may occur when the simultaneous connection. Referring to FIG. 4, a second processor converts a signal in a synchronization module or the like to connect to a slave device in a second processor system through a slave interface, transmits a signal to a second processor system, and waits for a completion signal. It is assumed that the processor also sends a signal to the slave device in the first processor system and waits for the completion signal through the slave, the master interface and the synchronization module. Since the second AHB bus determines that one master-slave relationship for transmitting the second processor transmitted signal is established, the second AHB bus is not connected to the first processor until the completion signal for the second processor access signal is transmitted. Can't send the completion signal. Thus, the first processor is in an unbounded standby state (40). Similarly, the first AHB bus cannot transmit the completion signal to the second processor for the same reason, so that the second processor is in an uninterrupted standby state (41). That is, the first processor and the second processor are waiting for each other only the completion signal, and because their connection command is not completed, each will be waiting for a random, which causes a serious malfunction.

5 is a diagram for explaining another embodiment of the present invention. An example of a method capable of preventing the malfunction described above with reference to FIG. 5 will be described.

The connection request signal is transmitted to the bridge module from the first and the second processors simultaneously or either (the first processor) (S50 and S51). In this case, in order to prevent simultaneous connection of the first and second processors, the bridge module transmits an error message to the second processor (S52). Communication to the processor that receives the error message from the bridge module is not performed. After the bridge module transmits the error message, the bridge module transmits a completion signal for the connection request of the first processor to the first processor (S53). In other words, only one master-slave relationship can be established through an error message, and the system can be executed without malfunction.

6 is a block diagram according to still another embodiment of the present invention. Another example of a method capable of preventing the malfunction described above will be described with reference to FIG. 6.

As in FIG. 1, the communication system of FIG. 6 includes first and second processor systems 61 and 66 for first and second processors and a bridge module 70 for communication between the two processor systems. The bridge module includes a master, a slave interface 62, 64, 67, 69, and a synchronization module 63, 68 for each processor system for data exchange between processor systems having different operating frequencies. The description of each processor system and the description of the same configuration are consistent with the description in FIG. 1. The bridge module according to the present embodiment includes not only the configuration described in FIG. 1 but also a connection control module 65 for mutually exclusive connection in order to prevent two processors from connecting at the same time. The connection control module implements a simple hardware semaphore function that can be shared by two processors to eliminate the above malfunction, that is, mutually exclusive connection. The semaphore function is a function capable of coordinating or synchronizing behavior in multiple processes that use resources competitively. Semaphores are values in designated storage that each process can see and change. Depending on the value of the semaphore being identified, if the process finds that the resource is immediately available or already in use by another process, it must wait some time before retrying. Semaphores use binary numbers (0 or 1), or may have additional values. Processes that use semaphores often have to check their values and change their values while using resources so that other semaphore users wait.

Hereinafter, a communication method for preventing a malfunction due to simultaneous connection through the connection control module 65 in which the semaphore function is implemented using a register will be described. When the register value is "0", it is assumed that the connection is possible, and when it is "1", it means that the connection is not possible.

First, the connection control module 65 is connected before performing data communication. When the value of the register is read and the value is " 0 ", it indicates a state in which a connection to the other party, that is, the second processor system is possible. Thus, the first processor transmits a connection command signal to the second processor system. At this time, the register value is automatically converted to "1". After the connection command is completed, the connection is converted back to a value of "0" to indicate completion of the connection.

When the first processor accesses the connection control module 65 to view the register value and the value is "1" before performing the data communication, when the value is converted to "0" because another processor is connecting. Wait until it changes to the value of "0" and then send the connection command signal.

7 shows a state transition diagram showing mutually exclusive connections to a semaphore register according to one embodiment of the invention.

As can be seen from the state transition diagram, if another processor (second processor) connects while one processor (first processor) is connecting to read a register value, the other processor (second processor) cannot read semaphore values. I have to wait. When the processor (first processor) in the register connection reads the value "0" (that is, when the other party has access to the system), the value of the semaphore register is automatically changed to "1", and the changed "1" value is awaited. Other processors (second processors) to read (that is, not gaining access to the other system) and prevent other processors (second processors) from gaining access to the other system (first processor system). . Therefore, the transmission instruction for the connection to the counterpart system only operates in one direction (from the first processor to the second processor system or from the second processor to the first processor system).

In addition, one processor (first processor) completes the connection to the other processor (second processor) system and makes the semaphore register value "0" (in other words, the connection completes), and the other processor (second If the processor attempts to read the semaphore register value, the changed "0" value can be read by another processor (the second processor).

That is, referring to the state transition diagram of FIG. 7, the first state is a state in which both the first and second processors are not connected, the second state is in communication with the first processor, and the second processor is in a standby state. In the third state, the second processor is connected and in communication, and the first processor is in a waiting state. If there is no connection request when both the first and second processors are not connected, the first state is maintained (A). In this case, when the first or second processor requests a connection, the first or second processor is converted to the second state or the third state, respectively (B and C). If the second processor is to be connected in the second state, the second state is maintained because the second processor must wait until the first processor connection is completed (H). When the first processor connection is completed, the state is converted to the first state in which the connection is possible (F). Similarly, in the third state, when the first processor attempts to connect in the third state, the third state is maintained (I), and when the connection to the second processor is completed, the state is converted to the first state (G).

Similarly, two processors can simultaneously access registers for semaphore functions. The problem that can arise in this case is when both processors recognize the semaphore register value as "0". In such a situation, the two processors think that the other processor is not connected and send a transmission command signal to the other system, which may cause the above-mentioned deadlock.

8 is a diagram for explaining a method for preventing simultaneous access to a register of a semaphore function.

 To avoid reading register values at the same time, simply wait for one processor while the other processor is reading the register values. Thus, when a register value for a semaphore is changing, it prevents other processors from reading the register value, that is, reading the "0" value at the same time. Of course, since the operating frequencies of the two processor systems are different, the register values are shared through the synchronization circuit for the semaphore register.

Referring to FIG. 8, a semaphore read command READ is transmitted to the register by the first processor. Send the command and wait 81 for one clock. If the result of reading the register reads a value of "0", it means that the connection is possible, and thus the register value is changed from "0" to "1" (83). If the second processor also transmits a semaphore read instruction (READ) to the register (85), the second processor accesses the register later than the instruction transmitted from the first processor by the synchronization circuit for the semaphore register. do. In this case, when the second processor reads a value in a situation 84 in which the first processor reads a register value and has not changed the value, the second processor also reads a value of "0". . Accordingly, when the second processor accesses a register, the second processor waits for a predetermined time while another processor accesses and reads a register value. After the first processor changes the register value, the second processor connects to read the value "1" so that the above problem does not occur (87).

That is, the interval from T0 to T1 is a state in which neither the first nor the second processor is connected. In the period from T1 to T2, the first processor is connected to read the value "0" of the register, and the second processor is in a waiting state. In the period from T2 to T3, the first processor terminates the register connection and is not connected to both the first and second processors. The interval from T3 to T4 is a state in which the second processor is connected and reading the value "1". In the period from T4 to T5, the second processor also terminates the register connection and neither the first nor the second processor is connected.

Those skilled in the art to which the present invention described above belongs will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. It is therefore to be understood that the embodiments described above are in all respects illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and from the same concept are to be construed as being included in the scope of the present invention will be.

According to the present invention, there is an effect that a simple direct connection can be made in two processor systems having different operating frequencies. In addition, it is possible to directly control the data transmission or the slave device in the counterpart system, which is convenient. In addition, the number of logic gates can be reduced to 1/5 compared to the conventional method, which can reduce costs and reduce the size of a system-on-chip (SOC).

Claims (13)

delete delete delete delete delete delete In a bridge module of a communication system for communication between processor systems using a bus operating at different operating frequencies, A synchronization module for converting an operating frequency of the first bus to an operating frequency of the second bus; A signal conversion module for converting a signal for transmitting the signal received at the first processor system to the second process system; A slave interface for transmitting a signal received from the first processor system to the synchronization module; And The master interface for receiving the signal converted the operating frequency through the synchronization module and transmits to the second processor system Including, the bridge module. The method of claim 7, wherein The bridge module further comprises a connection control module for controlling a simultaneous connection through the presence of a processor system that is currently connected. delete delete The method of claim 7, wherein The signal conversion module is implemented on the master interface. The method of claim 8, The connection control module includes a semaphore register having either a first value when the one of the first processor system and the second processor system has a connection and a second value when the connection is released. And a first value waits for a connection of the first processor system and the second processor system. The method of claim 12, The connection control module further includes a semaphore synchronization module for synchronizing an operating frequency when the first processor system and the second processor system connect to the semaphore register.

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