JP2616010B2 - Packet network - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet network for transferring packet format data including data and destination information indicating the destination.

[Conventional technology]

In a conventional packet network for transferring packet format data including data and transfer destination information, an exchange control unit for performing exchange control based on the transfer destination information included in the packet format data and each processing device are provided. The connection is made via a data signal line for transmission, a data signal line for reception, an input timing signal line, and an output timing signal line. When transmitting packet format data, each processing device connects to the input timing signal line. The switching control unit outputs the input timing signal and sends out the packet format data to the data signal line for transmission. The output timing signal is output via the output timing signal line to the And so as to transmit the packet format data.

[Problems to be solved by the invention]

Conventionally, as described above, each processing device and the exchange control unit are connected via a data signal line for transmission and a data signal line for reception, and transfer of packet format data is performed in one direction. There was a problem that the number of lines increased.

An object of the present invention is to reduce the number of data signal lines.

[Means for solving the problem]

In order to achieve the above object, the present invention comprises an exchange control unit and a plurality of processing devices connected to the exchange control unit, wherein each of the processing devices mutually includes transfer destination information via the exchange control unit. In a packet network for transmitting and receiving packet format data, a data signal line for each processing device capable of bidirectional transfer of packet format data, connecting the exchange control unit and each of the processing devices, and the exchange control unit And an input timing signal line for each of the processing devices, and an output timing signal line for each of the processing devices, for connecting the exchange control unit and the processing device. When transmitting the packet format data, the device determines that the state of the output timing signal line corresponding to its own processing device is used by the data signal line to output the packet format data. If not, the packet format data is output to the data signal line corresponding to the own processing device, and the state of the input timing signal line corresponding to the own processing device is input to the data signal line to input the packet format data. The exchange control unit is an input buffer for each of the processing devices, and is sent from the corresponding processing device via the data signal line. An input buffer for holding packet format data; an input buffer for each of the processing devices, an output buffer for holding packet format data to be sent to the corresponding processing device via the data signal line; In response to the transfer signal, the state of the input timing signal line corresponding to the own transfer permission circuit is changed to a state where the data signal line is a packet. The transfer of the packet format data is permitted by indicating that it is not used for inputting the format data and that the state of the output timing signal line corresponding to the own transfer permission circuit indicates that the output buffer is empty. A transfer permitting circuit, and holding the packet format data in each of the input buffers, thereby applying a transfer signal to a transfer permitting circuit corresponding to a processing device to which the packet format data is transferred, and A transfer circuit for transferring the packet format data to an output buffer corresponding to the processing device of the transfer destination by permitting the transfer, and holding the output data; and an output request circuit for each of the processing devices, which corresponds to its own output request circuit. Since the transfer of the packet format data is permitted by the transfer permission circuit, the output timing signal line corresponding to the own output request circuit is An output request circuit for outputting a force timing signal, and a direction control circuit for each of the processing devices, the output request circuit corresponding to the own direction control circuit based on the output timing signal output from the output request circuit corresponding to the own direction control circuit. A direction control circuit for controlling whether the data transfer direction of the data signal line to be transferred is from the processing device to the input buffer or from the output buffer to the processing device.

(Operation)

The packet format data sent via the data signal line is held in the input buffer. At this time, the input timing signal is being output to the input timing signal line. When the packet format data is held in the input buffer, the transfer circuit adds a transfer signal to a transfer permission circuit corresponding to the processing device to which the packet format data is transferred. The transfer permission circuit determines whether or not the transfer of the packet format data is permitted based on the states of the input timing signal line and the output timing signal line when the transfer signal is added. When the transfer of the packet format data is permitted by the transfer permission circuit, the transfer circuit transfers the packet format data to the output buffer corresponding to the processing device of the transfer destination, and the output request circuit transmits the output timing signal to the output timing signal line. Output. When the output timing signal is output, the direction control circuit sets the data transfer direction of the data signal line to the output direction, whereby the packet format data held in the output buffer is transferred via the data signal line.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which comprises a plurality of processing units 1-4 and an exchange control unit 5, both of which are data signal lines 10, 20, 30, 40 and input timing signals. Line 1
1, 21, 31, 41 and output timing signal lines 12, 22, 32, 42. When the output timing signals on the output timing signal lines 12, 22, 32, and 42 are active, the exchange control unit 5 changes the data transfer direction to the output buffers 15, 25, and 3.
Direction control circuits 13, 23, 33, 43 from processing devices 1 to 4 to input buffers 14, 24, 34, and 44 when not active; Input buffers 14, 24, 34, 44 for holding packet format data input from to 4, output buffers 15, 25, 35, 45 for holding packet format data to be output to each of the processing devices 1 to 4,
By adding the packet format data via the input buffers 14, 24, 34, 44, the transfer permission circuits 16, 26, 26 corresponding to the transfer destination indicated by the transfer destination information in the packet format data.
Output transfer signals 18, 28, 38, 48 to 36, 46 and transfer enable circuit 1
A transfer circuit 6 that transfers packet format data to output buffers 15, 25, 35, and 45 corresponding to transfer destinations by outputting permission signals 19, 29, 39, and 49 from 6, 26, 36, and 46, and a transfer permission Circuit 1
When the enable signals 19, 29, 39, and 49 are output from 6, 26, 36, and 46, the output timing signals to be output to the output timing signal lines 12, 22, 32, and 42 are activated to output the packet format data. Output request circuits 17,2 indicating that
The input timing signal lines 11, 21, 31, 41 and the output timing signal lines 12, 22, 32, 42 are checked by adding transfer signals 18, 28, 38, 48 from the transfer circuit 6, 7, 37, 47, and 47. , The data signal lines 10, 20, 30, 40 are not used for data input,
And a transfer permission circuit 1 that outputs permission signals 19, 29, 39, 49 by judging that the output buffers 15, 25, 35, 45 are empty.
6,26,36,46.

FIG. 2 is a time chart when the processing device 1 transfers packet format data to the processing device 3, and the operation will be described below with reference to the drawings.

When transferring the packet format data to the processing device 3, the processing device 1 confirms that the output timing signal 12 is not active, and then transfers the data and the processing device 3 of the transfer destination.
Is output to the data signal line 10 and the input timing signal output to the input timing signal line 11 is activated. Thereby, the packet format data output to the data signal line 10 is set in the input buffer 14 via the direction control circuit 13 and is applied to the transfer circuit 6. The transfer circuit 6 checks the transfer destination information in the packet format data added via the input buffer 14, and outputs a transfer signal to a transfer permission circuit corresponding to the transfer destination indicated by the transfer destination information. in this case,
Since the transfer destination information indicates the processing device 3, the transfer circuit 6
Outputs the transfer signal 38 to the transfer permission circuit 36 corresponding to the processing device 3.

When the transfer signal 38 is added, the transfer permission circuit 36 checks the input timing signal on the input timing signal line 31 and the output timing signal output from the output request circuit 37, and sets the data signal line 30 to the input of packet format data. The permission signal 39 is activated by confirming that it is not being used and that other packet format data is not being output (the output buffer 35 is empty). As a result, the transfer circuit 6 outputs the packet format data to the output buffer 35 corresponding to the processing device 3 which is the transfer destination, and
35 holds the packet format data output from the transfer circuit 6, and the output request circuit 37 activates the output timing signal output to the output timing signal line 32.

When the output timing signal on the output timing signal line 32 is activated, the data transfer direction of the direction control circuit 33 is from the output buffer 35 to the processing device 3, so that the packet format set in the output buffer 35 The data is transferred to the processing device 3 via the direction control circuit 33 and the data signal line 30. When the output timing signal, which is the output signal of the output request circuit 37, is activated, the transfer circuit 6 resets the transfer signal 38 and resets the transfer permission circuit 36.

In the above-described embodiment, the case where the packet format data is transferred from the processing device 1 to the processing device 3 has been described as an example. However, the transfer of the packet format data between other processing devices is performed in the same manner.

〔The invention's effect〕

As described above, since the present invention is designed to transfer packet format data bidirectionally using the same data signal line, there is an effect that the number of data signal lines can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of FIG. In the figure, 1 to 4... Processing apparatus, 5.
6: transfer circuit, 10, 20, 30, 40 ... data signal line, 11, 2
1,31,41 ... input timing signal lines, 12, 22, 32, 42 ... output timing signal lines, 13, 23, 33, 43 ... direction control circuits, 1
4, 24, 34, 44 ... input buffer, 15, 25, 35, 45 ... output buffer, 16, 26, 36, 46 ... transfer enable circuit, 17, 27, 37, 47 ...
… Output request circuit, 18, 28, 38, 48 …… Transfer signal, 19, 29, 39,
49 ... Enable signal.

Claims (1)

(57) [Claims] 1. An exchange control unit and a plurality of processing units connected to the exchange control unit, wherein each of the processing units transmits and receives packet format data including transfer destination information to and from each other via the exchange control unit. A data signal line for each processing device capable of bidirectional transfer of packet format data, connecting the exchange control unit and each of the processing devices, and the exchange control unit and the processing device. , An input timing signal line for each of the processing devices, and an output timing signal line for each of the processing devices, which connects the exchange control unit and the processing device. When transmitting data, the state of the output timing signal line corresponding to the own processing device indicates that the data signal line is not used to output packet format data. If it is, the packet format data is output to the data signal line corresponding to the own processing device, and the state of the input timing signal line corresponding to the own processing device is used to input the packet format data to the data signal line. The exchange control unit is an input buffer for each of the processing devices, and holds packet format data transmitted from the corresponding processing device via the data signal line. An input buffer, an output buffer for each of the processing devices, an output buffer for holding packet format data to be sent to the corresponding processing device via the data signal line, and a transfer permission circuit for each of the processing devices. In response to the transfer signal, the state of the input timing signal line corresponding to the self-transfer enable circuit and the data signal line are used to input the packet format data. A transfer permission circuit that indicates that the output buffer is not used, and that the state of the output timing signal line corresponding to the own transfer permission circuit indicates that the output buffer is empty, thereby permitting transfer of the packet format data. By holding the packet format data in each of the input buffers, a transfer signal is applied to a transfer permission circuit corresponding to the processing device to which the packet format data is transferred, and the transfer of the packet format data is permitted by the transfer permission circuit. A transfer circuit that transfers the packet format data to an output buffer corresponding to the processing device of the transfer destination and holds the data; and an output request circuit for each of the processing devices, the packet being transmitted by a transfer permission circuit corresponding to the output request circuit. By permitting the transfer of format data, the output timing signal is sent to the output timing signal line corresponding to the own output request circuit. An output request circuit for outputting the data signal line corresponding to the own direction control circuit based on an output timing signal output from the output request circuit corresponding to the own direction control circuit. A direction control circuit for controlling whether the data transfer direction is from the processing device to the input buffer or from the output buffer to the processing device.